鍨嬭櫉(h脿o)锛歑C5VLX50-3FFG324C
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銆�銆�宸ヨ棟锛�65nm
銆�銆�閭忚集鍠�鍏冩��(sh霉)锛氱磩5钀�(w脿n)
銆�銆�鏌ユ壘琛�锛圠UT锛夛細绱�25000鍊�(g猫)
銆�銆�瑙哥櫦(f膩)鍣�锛氱��50000鍊�(g猫)
銆�銆�DSP Slice鏁�(sh霉)閲忥細320鍊�(g猫)
銆�銆�Block RAM瀹归噺锛氱磩5.1Mb
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銆�銆�I/O Bank鏁�(sh霉)閲忥細18鍊�(g猫)
銆�銆�渚涢浕闆诲�擄細鏍稿績闆诲��0.9V锛孖/O闆诲��1.5V/1.8V/2.5V/3.3V
銆�銆�灏佽�濓細FFG324
銆�銆�閫熷害绛夌礆(j铆)锛�-3

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XC5VLX50T-3FFG324C
銆�銆�XC5VLX50-2FFG324C