鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng)
鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺
鏅傞枔锛�2022/10/20 10:18:41
闁辫畝锛�532
鐢�(ch菐n)鍝佸瀷铏� | XC5VLX50-2FFG1153C |
鎻忚堪 | 闆嗘垚闆昏矾FPGA 560 I / O 1153FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | Xilinx鍏徃 |
绯诲垪 | Virtex?-5LX |
鎵撳寘 | 鎵樼洡 |
闆诲-闆绘簮 | 0.95V?1.05V |
宸ヤ綔婧害 | 0掳C?85掳C(TJ) |
鍖呰/绠� | 1153-BBGA锛孎(xi脿n)CBGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁� | 1153-FCBGA(35x35) |
鍩烘湰闆朵欢铏� | XC5VLX50 |
鐢�(ch菐n)鍝佸瀷铏� | XC5VLX50-2FFG1153C |
鎻忚堪 | 闆嗘垚闆昏矾FPGA 560 I / O 1153FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | Xilinx鍏徃 |
绯诲垪 | Virtex?-5LX |
鎵撳寘 | 鎵樼洡 |
闆诲-闆绘簮 | 0.95V?1.05V |
宸ヤ綔婧害 | 0掳C?85掳C(TJ) |
鍖呰/绠� | 1153-BBGA锛孎(xi脿n)CBGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁� | 1153-FCBGA(35x35) |
鍩烘湰闆朵欢铏� | XC5VLX50 |
鍒堕�犲晢鍖呰瑾槑 | 35 X 35 MM锛岀劇閴�锛孎(xi脿n)BGA-1153 |
绗﹀悎姝愮洘RoHS | 鏄� |
鐙�鎱�(t脿i) | 娲绘�� |
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
鏈�澶ф檪閻橀牷鐜� | 1265.0鍏嗚但 |
JESD-30浠ｇ⒓ | S-PBGA-B1153 |
JESD-609浠ｇ⒓ | e1 |
CLB鏁�(sh霉)閲� | 3600.0 |
杓稿叆鏁�(sh霉)閲� | 560.0 |
閭忚集鍠厓鏁�(sh霉) | 46080.0 |
杓稿嚭鏁�(sh霉)閲� | 560.0 |
绔瓙鏁�(sh霉) | 1153 |
鏈�浣庡伐浣滄韩搴� | 0鈩� |
鏈�楂樺伐浣滄韩搴� | 85鈩� |
绲勭箶 | 3600 CLBS |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呰绛夋晥浠ｇ⒓ | BGA1153,34X34,40 |
鍖呰褰㈢媭 | 鍥涙柟褰� |
鍖呰褰㈠紡 | 缍�(w菐ng)鏍奸櫍鍒� |
宄板�煎洖娴佹韩搴�(鈩�) | 245 |
闆绘簮 | 1,2.5 |
搴ч珮 | 3.4姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲妯�(bi膩o)绋� | 1.0浼� |
鏈�灏忎緵闆婚浕澹� | 0.95浼� |
鏈�澶ч浕婧愰浕澹� | 1.05浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
婧害绛夌礆 | 鍏朵粬 |
绲傜瀹屾垚 | 閷�/閵�/閵�(Sn95.5Ag4.0Cu0.5) |
绲傜琛ㄦ牸 | 鐞� |
绔瓙闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶у��(绉�) | 30 |
闀峰害 | 35.0姣背 |
瀵害 | 35.0姣背 |
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