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XC5VLX50-1FFG1153C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪 FPGA 鑺墖涓殑涓�鍝°�俈irtex-5 绯诲垪鏄熀浜� 65nm 宸ヨ棟鍒堕�犵殑楂樻�ц兘 FPGA锛屽唬娉涙噳鐢ㄤ簬閫氫俊銆佷俊铏熻檿鐞嗐�佽闋诲拰鍦栧儚铏曠悊浠ュ強娓│娓噺绛夐牁鍩�銆傝┎鑺墖鍏峰倷璞愬瘜鐨勯倧杓硣婧�銆佸祵鍏ュ紡瀛樺劜鍣ㄥ銆佹暩(sh霉)瀛椾俊铏熻檿鐞嗗櫒 (DSP) 妯″锛屽苟鏀寔澶氱ó楂橀�熶覆琛屾帴鍙�銆�
銆�銆�Virtex-5 绯诲垪鍒嗙偤澶氬�嬪瓙绯诲垪锛孹C5VLX50 灞簬 LX 瀛愮郴鍒�锛屼富瑕侀潰鍚戦珮鎬у児姣�銆佷綆鍔熻�楃殑鎳夌敤鍫存櫙銆�
鍨嬭櫉锛歑C5VLX50-1FFG1153C
銆�銆�宸ヨ棟锛�65nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 50,000 鍊� Slice
銆�銆�Block RAM锛氱磩 3.1 Mb
銆�銆�DSP48 Slices锛�200 鍊�
銆�銆�I/O 寮曡叧鏁�(sh霉)锛�672
銆�銆�閰嶇疆妯″紡锛歋electMAP 鍜� Master/Slave SPI
銆�銆�灏佽椤炲瀷锛欶FG1153
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� 85掳C锛�
銆�銆�鏅傞悩闋荤巼锛氭渶楂樺彲閬� 550 MHz
XC5VLX50-1FFG1153C 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘鏋舵锛氶噰鐢� Virtex-5 鐨勭浜屼唬 ASMBL 鏋舵锛屾彁渚涙洿楂樼殑鎬ц兘鍜屾洿浣庣殑寤堕伈銆�
銆�銆�2. 鍏�(n猫i)缃� DSP 妯″锛氬寘鍚� 200 鍊� DSP48 Slice锛屽彲楂樻晥瀵︾従(xi脿n)寰╅洔鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗙畻娉曘��
銆�銆�3. 澶у閲� Block RAM锛�3.1 Mb 鐨勫垎甯冨紡瀛樺劜鍣ㄥ拰 Block RAM 璩囨簮锛岄仼鍚堟暩(sh霉)鎿�(j霉)绶╁瓨鍜� FIFO 鎳夌敤銆�
銆�銆�4. 鏀寔楂橀�熶覆琛屾敹鐧�(f膩)鍣細闆栫劧 LX 瀛愮郴鍒椾笉鍖呭惈楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛屼絾鍙互閫氶亷澶栭儴 PHY 鑺墖鎿村睍鍔熻兘銆�
銆�銆�5. 浣庡姛鑰楄ō瑷堬細閫氶亷 PowerDown 鍜屽嫊鎱�(t脿i)闆绘簮绠＄悊鎶�琛撻檷浣庡姛鑰椼��
銆�銆�6. 闈堟椿鐨� I/O 妯欐簴鏀寔锛氭敮鎸佸绋婧栧 LVCMOS銆丩VDS 鍜� SSTL锛屾豢瓒充笉鍚屾噳鐢ㄥ牬鏅渶姹傘��
銆�銆�7. 鍙潬鎬ч珮锛氭敮鎸佺郴绲�(t菕ng)鍏�(n猫i)鍙法绋�銆侀儴鍒嗛噸閰嶇疆绛夊姛鑳�锛屾彁鍗囪ō瑷堥潏娲绘�у拰鍙潬鎬�銆�
XC5VLX50-1FFG1153C 涓昏鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊瑷倷锛氬鍩虹珯銆佽矾鐢卞櫒銆佷氦鎻涙绛変腑鐨勪俊铏熻檿鐞嗗拰鍗�(xi茅)璀拌綁鎻�銆�
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細鐢ㄤ簬瀵︽檪瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓寮峰拰瑷堢畻姗熻瑕�銆�
銆�銆�3. 娓│鑸囨脯閲忥細鍦ㄨ嚜鍕曞寲娓│瑷倷涓綔鐐烘牳蹇冩帶鍒跺拰鏁�(sh霉)鎿�(j霉)铏曠悊鍠厓銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬閬嬪嫊鎺у埗銆佹鍣ㄨ瑕哄拰宸ュ粻鑷嫊鍖栫郴绲�(t菕ng)銆�
銆�銆�5. 閱�(y墨)鐧傝ō鍌欙細濡傝秴鑱叉垚鍍忋�丆T 鎺冩弿鍎�绛夐渶瑕侀珮鎬ц兘瑷堢畻鑳藉姏鐨勫牬鍚�銆�
銆�銆�6. 宓屽叆寮忚▓绠楋細鐐哄祵鍏ュ紡绯荤当(t菕ng)鎻愪緵闈堟椿鐨勭‖浠跺姞閫熷钩鑷恒��
XC5VLX30T-1FFG676C
銆�銆�XC5VLX30-1FFG676C
銆�銆�XC5VLX330T-1FFG1738C
