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鎮ㄥソ锛屾杩庝締(l谩i)鍒扮董搴�(k霉)闆诲瓙甯傚牬(ch菐ng)缍�(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺(c猫)

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩�(g貌u)缍�(w菐ng) > IC鐧剧 > XC5VLX50-1FF1153I

XC5VLX50-1FF1153I 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2025/4/28 17:15:12 鏌ョ湅 闁辫畝锛�40

XC5VLX50-1FF1153I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪锛團PGA锛変腑鐨勪竴鍝°�傝┎绯诲垪 FPGA 闈㈠悜楂樻�ц兘鍜岄珮瀵嗗害鎳�(y墨ng)鐢紝寤ｆ硾鎳�(y墨ng)鐢ㄤ簬閫氫俊銆佽埅绌鸿埅澶�銆侀啱(y墨)鐧傛垚鍍�銆佽闋昏檿鐞嗙瓑闋�(l菒ng)鍩�銆俋C5VLX50 鍩轰簬 65nm 宸ヨ棟鍒堕��锛屾彁渚涜睈瀵岀殑閭忚集璩囨簮銆佹暩(sh霉)瀛椾俊铏�(h脿o)铏曠悊锛圖SP锛夊姛鑳戒互鍙婂绋帴鍙ｉ伕闋�(xi脿ng)銆�
銆�銆�姝ゅ瀷铏�(h脿o)涓殑 XC 琛ㄧず Xilinx 鍏徃鐨� FPGA 鐢�(ch菐n)鍝佺窔(xi脿n)锛�5 琛ㄧず绗簲浠� Virtex 绯诲垪锛孷LX50 琛ㄧず鍏烽珨鑺墖鍨嬭櫉(h脿o)鍙婇倧杓柈鍏冭(gu墨)妯�锛�-1 琛ㄧず閫熷害绛夌礆(j铆)锛孎(xi脿n)F1153 琛ㄧず灏佽椤�(l猫i)鍨嬬偤 FineLine BGA 1153 寮曡叧锛孖 琛ㄧず鍟嗘キ(y猫)绱�(j铆)宸ヤ綔婧害鑼冨湇锛�0掳C 鑷� 85掳C锛夈��

鍙冩暩(sh霉)

閭忚集鍠厓锛氱磩 50,000
銆�銆�鏌ユ壘琛紙LUTs锛夛細绱� 29,491
銆�銆�瑙哥櫦(f膩)鍣細绱� 58,982
銆�銆�Block RAM锛氱磩 2,736 Kb
銆�銆�DSP Slice锛�192 鍊�(g猫)
銆�銆�I/O 鏁�(sh霉)閲忥細528
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丮aster/Slave SPI銆丅oundary Scan
銆�銆�宸ヨ棟鍒剁▼锛�65 nm
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹� 1.0V锛孖/O 闆诲 1.8V/2.5V/3.3V
銆�銆�宸ヤ綔婧害鑼冨湇锛�0掳C 鑷� 85掳C
銆�銆�灏佽锛欶ineLine BGA 1153 寮曡叧

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XC5VLX50 鎻愪緵浜嗗挤(qi谩ng)澶х殑閭忚集铏曠悊鑳藉姏鑸囬珮搴﹂泦鎴愮殑璩囨簮锛�
銆�銆�1. 鏀寔宓屽叆寮� DSP 鍔熻兘锛岄仼鐢ㄤ簬楂橀�熸暩(sh霉)鎿�(j霉)铏曠悊鍜屽京(f霉)闆滅畻娉曞(sh铆)鐝�(xi脿n)銆�
銆�銆�2. 鍏�(n猫i)缃ぇ瀹归噺 Block RAM锛屾敮鎸侀珮鏁堢殑鏁�(sh霉)鎿�(j霉)瀛樺劜(ch菙)鑸囩珐瀛樻搷浣�銆�
銆�銆�3. 鎿佹湁闈堟椿鐨� I/O 妯�(bi膩o)婧�(zh菙n)鍏煎鎬�锛屽彲杓曟澗閫ｆ帴澶栭儴瑷�(sh猫)鍌欐垨绯荤当(t菕ng)銆�
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銆�銆�5. 闆嗘垚浜� PowerPC 铏曠悊鍣ㄧ‖鏍搁伕闋�(xi脿ng)锛堝儏闄愮壒瀹氬瀷铏�(h脿o)锛夛紝鍙敤浜庢贩鍚堢‖浠�/杌熶欢鏋舵(g貌u)銆�
銆�銆�6. 鏀寔楂樼礆(j铆)鏅�(sh铆)閻樼鐞嗘ā濉婏紙DCM 鍜� PLL锛�锛岀⒑淇濈簿纰虹殑鏅�(sh铆)搴忔帶鍒�銆�
銆�銆�7. 鍏峰倷浣庡姛鑰楀劒(y艒u)鍖栧姛鑳�锛岄仼鍚堝皪(du矛)鑳借�楁晱鎰熺殑鎳�(y墨ng)鐢ㄥ牬(ch菐ng)鏅�銆�

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XC5VLX50 鐨勫唬娉涙噳(y墨ng)鐢ㄩ牁(l菒ng)鍩熷寘鎷絾涓嶉檺浜庯細
銆�銆�1. 閫氫俊瑷�(sh猫)鍌欙細濡傜劇(w煤)绶�(xi脿n)鍩虹珯銆佽矾鐢卞櫒銆佷氦鎻涙(j墨)绛夛紝鐢ㄤ簬鍗�(xi茅)璀拌檿鐞嗗拰淇¤櫉(h脿o)瑾�(di脿o)鍒惰В瑾�(di脿o)銆�
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銆�銆�4. 閱�(y墨)鐧傝ō(sh猫)鍌欙細濡傝秴鑱叉尝鎴愬儚銆丆T 鎺冩弿鍎�锛岃矤(f霉)璨�(z茅)蹇�熸暩(sh霉)鎿�(j霉)铏曠悊鑸囧湒鍍忛噸寤�銆�
銆�銆�5. 鑸┖鑸ぉ锛氱敤浜庡皫(d菐o)鑸郴绲�(t菕ng)銆佽(w猫i)鏄熼�氫俊锛屽叿鍌欓珮鍙潬鎬ц垏鎶楄蓟灏勮兘鍔�銆�
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鏇夸唬鍨嬭櫉(h脿o)

XC5VLX30T-1FF1136I
銆�銆�XC5VLX330T-1FF1739I
銆�銆�XC5VSX50T-1FF1136I

xc5vlx50-1ff1153i鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

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  • 灏佽/鎵硅櫉(h脿o)
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xc5vlx50-1ff1153i鐢�(ch菐n)鍝�

xc5vlx50-1ff1153i鍙冩暩(sh霉)

  • 妯�(bi膩o)婧�(zh菙n)鍖呰1
  • 椤�(l猫i)鍒�闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪锛�
  • 绯诲垪Virtex®-5 LX
  • LAB/CLB鏁�(sh霉)3600
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)46080
  • RAM 浣嶇附瑷�(j矛)1769472
  • 杓稿叆/杓稿嚭鏁�(sh霉)560
  • 闁�(m茅n)鏁�(sh霉)-
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  • 瀹夎椤�(l猫i)鍨�琛ㄩ潰璨艰
  • 宸ヤ綔婧害-40°C ~ 100°C
  • 灏佽/澶栨1153-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�1153-FCBGA锛�35x35锛�
  • 閰嶇敤568-5088-ND - BOARD DEMO DAC1408D750HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1153-500-G-ND - BOARD DEV VIRTEX 5 FF1153HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET122-1508-ND - EVALUATION PLATFORM VIRTEX-5