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闁辫畝锛�30
XC5VLX330-2FFG1760I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏熴�俈irtex-5 绯诲垪鍩轰簬 65nm 宸ヨ棟鎶�琛�(sh霉)鍒堕��锛屾彁渚涗簡楂樻�ц兘銆侀珮瀵嗗害閭忚集璩囨簮鍜岃睈瀵岀殑宓屽叆寮忓姛鑳芥ā濉�锛岄仼鐢ㄤ簬閫氫俊銆佽埅绌鸿埅澶�銆佸湅闃层�侀啱(y墨)鐧傛垚鍍忎互鍙婂叾浠栭珮鎬ц兘瑷堢畻闋樺煙銆�
銆�銆�Virtex-5 绯诲垪鍒嗙偤澶氬�嬪瓙绯诲垪锛屽寘鎷� LX锛堥�氱敤锛�銆丩XT锛堥�氱敤+涓茶鏀剁櫦(f膩)鍣級銆丼XT锛堜俊铏熻檿鐞�+涓茶鏀剁櫦(f膩)鍣級绛�銆俋C5VLX330 灞簬 LX 瀛愮郴鍒�锛屼富瑕侀嚌灏嶉珮閭忚集瀵嗗害鍜岄珮鎬ц兘鎳夌敤瑷▓銆�
鍨嬭櫉锛歑C5VLX330-2FFG1760I
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歏irtex-5 LX
銆�銆�宸ヨ棟锛�65nm
銆�銆�閫熷害绛夌礆锛�-2
銆�銆�I/O 鏁�(sh霉)閲忥細940
銆�銆�閰嶇疆妯″紡锛歋electMAP, Master SPI, Slave SPI
銆�銆�灏佽锛欶FG1760
銆�銆�鍏�(n猫i)鏍搁浕澹擄細1.0V
銆�銆�I/O 闆诲锛�1.8V/2.5V/3.3V
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 332,000
銆�銆�Block RAM锛氱磩 12.5MB
銆�銆�DSP Slice锛氱磩 1,080
XC5VLX330-2FFG1760I 鎻愪緵浜嗘サ楂樼殑閭忚集璩囨簮瀵嗗害鍜岄潏娲荤殑鍙法绋嬭兘鍔涳紝鏀寔澶氱ó宓屽叆寮忕‖鏍� IP 妯″锛屼緥濡� PowerPC 铏曠悊鍣ㄣ�丳CI Express 鎺у埗鍣�銆佸崈鍏嗕互澶恫(w菐ng) MAC 鍜屽姞瀵嗘ā濉婄瓑銆�
銆�銆�瑭茶姱鐗囧叿鏈夊挤澶х殑 DSP 鍔熻兘锛岄�氶亷澶ч噺闆嗘垚鐨� DSP Slice 鍙鐝�(xi脿n)楂樻晥鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�銆�
銆�銆�鍏堕珮閫熶覆琛屾敹鐧�(f膩)鍣紙鍦� LXT/SXT 瀛愮郴鍒椾腑鍙敤锛夎兘澶犳敮鎸侀珮閬� 6.5Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼锛屼絾姝ゅ瀷铏熷爆浜� LX 瀛愮郴鍒�锛屼笉鍖呭惈涓茶鏀剁櫦(f膩)鍣ㄥ姛鑳�銆�
銆�銆�姝ゅ锛岃┎鑺墖閭勬敮鎸佸绋厤缃柟寮�锛屽寘鎷緸 Flash 鍟熷嫊鎴栭�氶亷澶栭儴涓绘閫茶鍕曟厠(t脿i)鍔犺級銆�
銆�銆�鐢变簬閲囩敤浜嗗厛閫茬殑 65nm 宸ヨ棟锛岃姱鐗囧叿鍌欒純浣庣殑鍔熻�楀拰杓冮珮鐨勬�ц兘琛ㄧ従(xi脿n)锛岄潪甯搁仼鍚堝皪璩囨簮闇�姹傝純楂樹笖瑕佹眰浣庡姛鑰楃殑鎳夌敤鍫存櫙銆�
XC5VLX330-2FFG1760I 涓昏鎳夌敤浜庨渶瑕侀珮閭忚集瀵嗗害鍜岄珮鎬ц兘鐨勫牬鍚�锛屽寘鎷絾涓嶉檺浜庯細
銆�銆�1. 楂樼閫氫俊瑷倷锛屽璺敱鍣�銆佷氦鎻涙鍜屽熀绔�;
銆�銆�2. 閱�(y墨)鐧傛垚鍍忚ō鍌欙紝濡� CT 鎺冩弿鍎�鍜岃秴鑱叉尝瑷倷;
銆�銆�3. 杌嶄簨鍜岃埅绌鸿埅澶╅牁鍩�锛屼緥濡傞浄閬旂郴绲�(t菕ng)鍜岃(w猫i)鏄熼�氫俊;
銆�銆�4. 娓│鑸囨脯閲忓剙鍣紝濡傜ず娉㈠櫒鍜岄牷璀滃垎鏋愬剙;
銆�銆�5. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�熷崱锛岀敤浜庢鍣ㄥ缈掓帹鐞嗘垨澶ф暩(sh霉)鎿�(j霉)铏曠悊;
銆�銆�6. 瑕栭牷寤ｆ挱绯荤当(t菕ng)锛屽瀵︽檪绶ㄧ⒓瑙ｇ⒓鍜屽湒鍍忚檿鐞�銆�
銆�銆�閫欎簺鎳夌敤鍫存櫙鍏呭垎鍒╃敤浜� XC5VLX330 鐨勫ぇ瀹归噺閭忚集璩囨簮銆侀珮鏁� DSP 鎬ц兘浠ュ強闈堟椿鐨勫瑷帴鍙�銆�
XC5VLX330T-2FFG1760I
