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鎮ㄥソ锛屾杩庝締鍒扮董搴�(k霉)闆诲瓙甯傚牬(ch菐ng)缍�(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺(c猫)

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩�(g貌u)缍�(w菐ng) > IC鐧剧 > XC5VLX330-1FFG1760I

XC5VLX330-1FFG1760I 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2025/5/22 16:31:50 鏌ョ湅 闁辫畝锛�17

XC5VLX330-1FFG1760I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪 FPGA 涓殑涓�娆鹃珮鎬ц兘鍣ㄤ欢銆傝┎绯诲垪鍩轰簬 65nm 鍒剁▼宸ヨ棟锛屾彁渚涘挤(qi谩ng)澶х殑閭忚集璩囨簮銆佽睈瀵岀殑 DSP Slice 鍜屽祵鍏ュ紡瀛樺劜(ch菙)鍣ㄦā濉�锛屽唬娉涢仼鐢ㄤ簬閫氫俊銆佷俊铏�(h脿o)铏曠悊銆佸湒鍍忚檿鐞嗐�佸伐妤�(y猫)鎺у埗绛夐牁(l菒ng)鍩熺殑寰�(f霉)闆滆ō(sh猫)瑷�(j矛)闇�姹�銆�
銆�銆�XC5VLX330 鏄� Virtex-5 LX 瀹舵棌涓殑涓�鍝�锛屼富瑕侀嚌灏�(du矛)浣庢垚鏈拰浣庡姛鑰楁噳(y墨ng)鐢ㄥ劒(y艒u)鍖栵紝鍚屾檪(sh铆)浠嶇劧淇濇寔浜嗚純楂樼殑鎬ц兘姘村钩銆�

鍙冩暩(sh霉)

绯诲垪锛歏irtex-5 LX
銆�銆�鍨嬭櫉(h脿o)锛歑C5VLX330-1FFG1760I
銆�銆�鍒剁▼宸ヨ棟锛�65nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細332,800
銆�銆�DSP Slice 鏁�(sh霉)閲忥細960
銆�銆�Block RAM 绺介噺锛�4,608 Kb
銆�銆�I/O 鏁�(sh霉)閲忥細768
銆�銆�閰嶇疆妯″紡锛歋electMAP, Master/Slave Serial, Boundary Scan
銆�銆�灏佽椤炲瀷锛欶FG1760
銆�銆�閫熷害绛夌礆(j铆)锛�-1

鐗规��

XC5VLX330-1FFG1760I 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樺瘑搴﹂倧杓硣婧愶紝鏀寔寰�(f霉)闆滅殑绠楁硶瀵�(sh铆)鐝�(xi脿n)鍜岀郴绲�(t菕ng)闆嗘垚銆�
銆�銆�2. 鍏�(n猫i)缃殑 DSP Slice 鎻愪緵楂樻晥鐨勬暩(sh霉)瀛椾俊铏�(h脿o)铏曠悊鑳藉姏锛岄仼鍚堟烤娉�銆丗FT 鍜岀煩闄ｉ亱(y霉n)绠楃瓑浠诲嫏(w霉)銆�
銆�銆�3. 澶у閲忕殑宓屽叆寮� Block RAM 鏀寔?j菒n)?sh霉)鎿�(j霉)绶╂矕鍜� FIFO 鎳�(y墨ng)鐢�銆�
銆�銆�4. 鏀寔澶氱ó楂橀�熶覆琛屾帴鍙ｏ紙濡� RocketIO锛�锛屽彲瀵�(sh铆)鐝�(xi脿n)楂橀仈(d谩) 6.5Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼銆�
銆�銆�5. 闆嗘垚鐨� PowerPC 纭牳铏曠悊鍣紙鍦ㄦ煇浜涘瓙绯诲垪涓級鍙互鐢ㄤ簬宓屽叆寮忕郴绲�(t菕ng)瑷�(sh猫)瑷�(j矛)銆�
銆�銆�6. 鏀寔闈堟椿鐨勬檪(sh铆)閻樼鐞嗗姛鑳�锛屽寘鎷� PLL 鍜� DCM 妯″銆�
銆�銆�7. 鎻愪緵璞愬瘜鐨勮(di脿o)瑭﹀拰瑷烘柗宸ュ叿锛屽 ChipScope 鍜屽湪绶氶噸閰嶇疆鍔熻兘銆�
銆�銆�8. 绗﹀悎 RoHS 妯�(bi膩o)婧�(zh菙n)锛岄仼鐢ㄤ簬鐠�(hu谩n)淇濊姹傚毚(y谩n)鏍肩殑鍫�(ch菐ng)鏅�銆�

鎳�(y墨ng)鐢�

瑭茶姱鐗囬仼鐢ㄤ簬浠ヤ笅鎳�(y墨ng)鐢ㄥ牬(ch菐ng)鏅細
銆�銆�1. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂�锛屽鍩虹珯鏀剁櫦(f膩)淇℃(j墨)銆佽矾鐢卞櫒鍜屼氦鎻涙(j墨)涓殑鏁�(sh霉)鎿�(j霉)鍖呰檿鐞�銆�
銆�銆�2. 楂橀�熶俊铏�(h脿o)铏曠悊闋�(l菒ng)鍩�锛屼緥濡傞浄閬�(d谩)淇¤櫉(h脿o)铏曠悊銆侀煶闋�/瑕栭牷绶ㄨВ纰�銆�
銆�銆�3. 閱�(y墨)鐧傝ō(sh猫)鍌欎腑鐨勫湒鍍忛噰闆嗚垏铏曠悊锛屽瓒呰伈娉㈣ō(sh猫)鍌欐垨 CT 鎺冩弿鍎�銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊(d貌ng)鍖栦腑鐨勫(sh铆)鏅�(sh铆)鎺у埗鍜岄亱(y霉n)鍕�(d貌ng)鎺у埗銆�
銆�銆�5. 娓�(c猫)瑭﹁垏娓�(c猫)閲忚ō(sh猫)鍌�锛屽绀烘尝鍣ㄥ拰闋昏瓬鍒嗘瀽鍎�銆�
銆�銆�6. 鑸┖鑸ぉ闋�(l菒ng)鍩熶腑鐨勯珮鍙潬鎬у祵鍏ュ紡瑷�(j矛)绠楀钩鑷�(t谩i)銆�

鏇夸唬鍨嬭櫉(h脿o)

XC5VLX330T-1FFG1760I
銆�銆�XC5VLX330-2FFG1760I
銆�銆�XC5VLX330T-2FFG1760I

xc5vlx330-1ffg1760i鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�(h脿o)
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉(h脿o)
  • 瑭㈠児(ji脿)

xc5vlx330-1ffg1760i鍙冩暩(sh霉)

  • 妯�(bi膩o)婧�(zh菙n)鍖呰1
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛�
  • 绯诲垪Virtex®-5 LX
  • LAB/CLB鏁�(sh霉)25920
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)331776
  • RAM 浣嶇附瑷�(j矛)10616832
  • 杓稿叆/杓稿嚭鏁�(sh霉)1200
  • 闁�鏁�(sh霉)-
  • 闆绘簮闆诲0.95 V ~ 1.05 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害-40°C ~ 100°C
  • 灏佽/澶栨1760-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�1760-FCBGA
  • 閰嶇敤568-5088-ND - BOARD DEMO DAC1408D750HW-V5-ML525-UNI-G-ND - EVAL PLATFORM ROCKET IO VIRTEX-5HW-AFX-FF1760-500-G-ND - BOARD DEV VIRTEX 5 FF1760