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XC5VLX30T-1FFG323C鏄疿ilinx鍏徃鎺ㄥ嚭鐨刅irtex-5绯诲垪FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛変腑鐨勪竴鍝°�傝┎鍣ㄤ欢鍩轰簬65nm宸ヨ棟鎶�琛�锛屽叿鏈夐珮閭忚集瀵嗗害銆佽睈瀵岀殑宓屽叆寮忓瓨鍎插櫒鍜孌SP妯″锛屼互鍙婂挤澶х殑浜掗�ｈ兘鍔涳紝閬╁悎鐢ㄤ簬楂樻�ц兘瑷堢畻銆侀�氫俊绯荤当(t菕ng)銆佸湒鍍忚檿鐞嗙瓑闋樺煙銆�
銆�銆�瑭插瀷铏熶腑鐨�'XC5VLX30T'琛ㄧず灞簬Virtex-5 LX绯诲垪锛岃(gu墨)妯＄偤30T锛堝ぇ绱�3钀倧杓柈鍏冿級銆�'-1'琛ㄧず閫熷害绛夌礆鐐�-1锛岃��'FFG323C'鍓囪〃绀哄皝瑁濆舰寮忕偤FFG323锛屽伐浣滄韩搴﹁寖鍦嶇偤鍟嗘キ(y猫)绱氾紙C锛�銆�
鍨嬭櫉锛歑C5VLX30T-1FFG323C
銆�銆�绯诲垪锛歏irtex-5 LX
銆�銆�閭忚集鍠厓鏁�(sh霉)锛氱磩30,000
銆�銆�閰嶇疆闁冨瓨锛氫笉闆嗘垚
銆�銆�IO寮曡叧鏁�(sh霉)锛�323
銆�銆�灏佽锛欶FG323
銆�銆�閫熷害绛夌礆锛�-1
銆�銆�宸ヨ棟锛�65nm
銆�銆�鍏�(n猫i)鏍搁浕澹擄細1.0V
銆�銆�I/O闆诲锛�1.8V/2.5V/3.3V
銆�銆�宸ヤ綔婧害鑼冨湇锛�0掳C 鑷� 85掳C
銆�銆�瀛樺劜鍣細鍖呭惈Block RAM 鍜� Distributed RAM
銆�銆�DSP Slice锛氭敮鎸�
銆�銆�鍔熻�楋細瑕栧叿楂旇ō瑷堣�屽畾
XC5VLX30T-1FFG323C鍏峰倷浠ヤ笅涓昏鐗规�э細
銆�銆�1. 楂樻�ц兘鏋舵锛氬熀浜嶸irtex-5 FPGA鏋舵锛屾彁渚涘挤澶х殑閭忚集铏曠悊鑳藉姏鍜岄潏娲荤殑璩囨簮閰嶇疆銆�
銆�銆�2. 宓屽叆寮忓瓨鍎插櫒锛氶泦鎴愪簡Block RAM鍜孌istributed RAM锛岀敤浜庢暩(sh霉)鎿�(j霉)绶╂矕鍜屽瓨鍎�锛屾豢瓒冲京闆滅畻娉曠殑闇�姹�銆�
銆�銆�3. DSP Slice锛氬収(n猫i)缃皥鐢ㄦ暩(sh霉)瀛椾俊铏熻檿鐞嗗櫒浠�锛岄仼鐢ㄤ簬楂橀�熶俊铏熻檿鐞嗕换鍕�銆�
銆�銆�4. 鏀寔澶氱ó鎺ュ彛妯欐簴锛氬PCI Express銆丼erial RapidIO绛�锛屼究浜庤垏澶栭儴瑷倷閫氫俊銆�
銆�銆�5. 浣庡姛鑰楀劒(y艒u)鍖栵細閫氶亷鍏堥�茬殑65nm宸ヨ棟鍜屽嫊鎱�(t脿i)鍔熻�楃鐞嗘妧琛撻檷浣庢暣楂旇兘鑰�銆�
銆�銆�6. 寤ｆ硾鐨勬噳鐢ㄥ牬鏅細閬╃敤浜庨�氫俊銆佽粛宸�銆侀啱(y墨)鐧傚奖鍍�銆佸伐妤�(y猫)鑷嫊鍖栫瓑澶氬�嬮牁鍩�銆�
XC5VLX30T-1FFG323C寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊绯荤当(t菕ng)锛氬寘鎷熀绔�銆佽矾鐢卞櫒銆佷氦鎻涙绛夐渶瑕侀珮甯跺鍜屽鏅傝檿鐞嗚兘鍔涚殑瑷倷銆�
銆�銆�2. 鍦栧儚铏曠悊锛氬瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓寮风瓑銆�
銆�銆�3. 鏁�(sh霉)鎿�(j霉)涓績锛氱敤浜庡姞閫熸湇鍕欏櫒涓殑鐗瑰畾瑷堢畻浠诲嫏銆�
銆�銆�4. 宸ユキ(y猫)鎺у埗锛氬鐝�(xi脿n)寰╅洔鐨勫鏅傛帶鍒堕倧杓�銆�
銆�銆�5. 閱�(y墨)鐧傝ō鍌欙細渚嬪瓒呰伈娉㈡垚鍍忓剙銆丆T鎺冩弿鍎�绛夊皪鏁�(sh霉)鎿�(j霉)铏曠悊閫熷害瑕佹眰杓冮珮鐨勫牬鍚堛��
XC5VLX30T-1FFG676C
銆�銆�XC5VLX30T-1FFG796C
