鍨嬭櫉锛歑C5VLX30T-1FF665C
銆�銆�宸ヨ棟锛�65nm
銆�銆�鍏�(n猫i)鏍搁浕澹擄細1.0V
銆�銆�I/O 闆诲�擄��1.8V / 2.5V / 3.3V
銆�銆�閭忚集鍠�鍏冩��(sh霉)锛氱磩 3 钀�
銆�銆�RAM 瀹归噺锛�1,760 Kb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細240
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丮aster/Slave SPI銆丅PI銆丗PGA 澶栭儴瀛樺劜鍣�
銆�銆�灏佽�濓細FFG665 (665 寮曡叧 Flip-Chip BGA)
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏細宸ユ��(y猫)绱氾紙-40掳C 鑷� +85掳C锛�
銆�銆�閫熷害绛夌礆锛�-1锛堟渶蹇�锛�

XC5VLX30T-1FF665C 鎻愪緵鍗撹秺鐨勬�ц兘鍜岄潏娲绘�э紝閬╁悎鐢ㄤ簬闇�瑕佸ぇ閲忓彲绶ㄧ▼閭忚集鐨勬噳(y墨ng)鐢ㄥ牬鏅�銆備互涓嬫槸鍏朵富瑕佺壒鎬э細
銆�銆�1. 楂樻�ц兘鏋舵��(g貌u)锛氶噰鐢ㄧ��浜屼唬 ASMBL锛圓dvanced Square Macro Block Logic锛夌祼(ji茅)妲�(g貌u)锛屾敮鎸侀珮閬�(d谩) 533 MHz 鐨勭郴绲�(t菕ng)鏅傞悩闋荤巼銆�
銆�銆�2. 宓屽叆寮忓瓨鍎插櫒锛氶泦鎴愪簡澶ч噺鐨� Block RAM锛屽彲鐢ㄤ簬瀵︾従(xi脿n) FIFO銆佺珐瀛樹互鍙婂叾浠栧瓨鍎查渶姹�銆�
銆�銆�3. DSP 鍔熻兘锛氬収(n猫i)缃� DSP48A1 Slice锛屾瘡鍊� Slice 鍖呭惈涓�鍊� 18脳18 浣嶄箻娉曞櫒鍜屼竴鍊� 48 浣嶅姞娉�/绱�鍔犲��锛岄潪甯搁仼鍚堟暩(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�(w霉)銆�
銆�銆�4. 鍙�鎿�(ku貌)灞� I/O锛氭敮鎸佸�氱ó妯�(bi膩o)婧�(zh菙n) I/O 鍗�(xi茅)璀�锛屽寘鎷� LVCMOS銆丩VDS 鍜� SSTL锛屾豢瓒冲�氭ǎ鍖栫殑閫ｆ帴闇�姹傘��
銆�銆�5. 鍏�(n猫i)缃�鏅傞悩绠＄悊锛氶泦鎴� DCM锛圖igital Clock Manager锛夊拰 PLL锛圥hase-Locked Loop锛�锛屾彁渚涚簿纰虹殑鏅傞悩鍒嗛牷鍜屽�嶉牷鍔熻兘銆�
銆�銆�6. 閰嶇疆閬搁爡璞愬瘜锛氭敮鎸佸�氱ó閰嶇疆妯″紡锛屼究浜庢牴鎿�(j霉)瀵﹂殯闇�姹傞伕鎿囨渶鍚堥仼鐨勫姞杓夋柟寮�銆�
銆�銆�7. 浣庡姛鑰楄ō(sh猫)瑷堬細閫氶亷 PowerPC 鎶�琛�(sh霉)鍎�(y艒u)鍖栵紝纰轰繚鍦ㄩ珮闋婚亱(y霉n)琛屾檪浠嶇劧淇濇寔杓冧綆鐨勮兘鑰楁按骞�銆�
銆�銆�8. 楂樺彲闈犳�э細缍�(j墨ng)閬庡毚(y谩n)鏍肩殑娓�瑭﹀拰绡╅伕锛岄仼鐢ㄤ簬灏嶇��(w臎n)瀹氭�ц�佹眰妤甸珮鐨勫伐妤�(y猫)鍜岃粛宸ラ牁(l菒ng)鍩�銆�

XC5VLX30T-1FF665C 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 閫氫俊瑷�(sh猫)鍌欙細濡傝矾鐢卞櫒銆佷氦鎻涙��(j墨)銆佸熀绔欏拰鍏朵粬楂橀�熸暩(sh霉)鎿�(j霉)鍌宠几瑷�(sh猫)鍌�銆�
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細鐢ㄤ簬瀵︽檪鍦栧儚閲囬泦銆佸垎鏋愬拰椤�绀�锛屼緥濡傞啱(y墨)鐧傛垚鍍忋�佸畨闃茬洠(ji膩n)鎺х瓑銆�
銆�銆�3. 娓�瑭﹁垏娓�閲忥細浣滅偤鏍稿績鎺у埗鍠�鍏冿紝瀹屾垚寰�(f霉)闆滄尝褰㈢敓鎴愬拰淇¤櫉鍒嗘瀽銆�
銆�銆�4. 宸ユキ(y猫)鑷�鍕曞寲锛氱敤浣滈��(y霉n)鍕曟帶鍒�銆佹��(j墨)鍣ㄤ汉鎶�琛�(sh霉)鍙婂伐寤犳祦姘寸窔涓�鐨勯��(gu膩n)閸甸倧杓�鎺у埗鍣ㄣ��
銆�銆�5. 姹借粖闆诲瓙锛氭敮鎸侀珮绱氶�曢�涜紨鍔╃郴绲�(t菕ng)锛圓DAS锛夊拰杌婅級淇℃伅濞涙▊绯荤当(t菕ng)鐨勯枊鐧�(f膩)銆�
銆�銆�6. 鑸�绌鸿埅澶╄垏鍦嬮槻锛氱敱浜庡叾鎶楄蓟灏勮兘鍔�锛岄仼鐢ㄤ簬琛�(w猫i)鏄熼�氫俊銆侀浄閬�(d谩)绯荤当(t菕ng)浠ュ強灏�(d菐o)褰堝埗灏�(d菐o)绛夐牁(l菒ng)鍩熴��

XC5VLX30T-1FFG665I
銆�銆�XC5VLX30T-1FFG665C
銆�銆�XC5VLX30T-2FFG665C