鏅傞枔锛�2022/10/20 10:20:43
闁辫畝锛�652
鐢�(ch菐n)鍝佸瀷铏� | XC5VLX30-2FFG324I |
鎻忚堪 | IC FPGA 220 I/O 324FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢�(ch菐n)鍝佸瀷铏� | XC5VLX30-2FFG324I |
鎻忚堪 | IC FPGA 220 I/O 324FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢熺敘(ch菐n)寤犲 | Xilinx鍏徃 |
绯诲垪 | Virtex?-5 LX |
閮ㄥ垎鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 0.95V~1.05V |
宸ヤ綔婧害 | -40掳C~100掳C(TJ) |
鍖�/绠� | 324-BBGA锛孎(xi脿n)CBGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘 | 324-FCBGA(19x19) |
鍩虹(ch菙)閮ㄤ欢铏� | XC5VLX30 |
浜斿�嬪钩鑷篖X锛孡XT锛孲XT锛孴XT鍜孎XT
銆俈irtex-5 LX锛氶珮鎬ц兘閫氱敤閭忚集鎳�(y墨ng)鐢�
銆俈irtex-5 LXT锛氬叿鏈夐珮绱氫覆琛岄�ｆ帴鐨勯珮鎬ц兘閭忚集
銆俈irtex-5 SXT锛氬叿鏈夐珮绱氫覆琛岄�ｆ帴鐨勯珮鎬ц兘淇¤櫉铏曠悊鎳�(y墨ng)鐢�
銆俈irtex-5 TXT锛氬叿鏈夐洐瀵嗗害楂樼礆涓茶閫ｆ帴鐨勯珮鎬ц兘绯荤当(t菕ng)
銆俈irtex-5 FXT锛氬叿鏈夐珮绱氫覆琛岄�ｆ帴鐨勯珮鎬ц兘宓屽叆寮忕郴绲�(t菕ng)
璺ㄥ钩鑷哄吋瀹规��
銆侺XT锛孲XT鍜孎XT鍣ㄤ欢閲囩敤鍙(di脿o)闆诲瑾�(di脿o)绡�(ji茅)鍣紝鍦ㄥ悓涓�灏佽涓吋瀹�
鏈�鍏堥��锛岄珮鎬ц兘锛屾渶浣冲埄鐢ㄧ巼鐨凢PGA鏋舵(g貌u)
銆傜湡姝ｇ殑6杓稿叆鏌ユ壘琛�(LUT)鎶�琛�(sh霉)
銆傞洐5-LUT閬搁爡
銆傛敼閫茬殑娓涘皯璺宠簫璺敱
銆�64浣嶅垎甯冨紡RAM閬搁爡
銆係RL32 / Dual SRL16閬搁爡
寮峰ぇ鐨勬檪閻樼鐞嗙璨�(CMT)鏅傞悩
銆傛暩(sh霉)瀛楁檪閻樼鐞嗗櫒(DCM)闃绘闆跺欢閬茬珐娌�锛岄牷鐜囧悎鎴愬拰鏅傞悩鐩哥Щ
銆侾LL妯″鐢ㄤ簬杓稿叆鎶栧嫊婵炬尝锛岄浂寤堕伈绶╂矕锛岄牷鐜囧悎鎴愬拰鐩镐綅鍖归厤鏅傞悩鍒嗛牷
36-Kbit Block RAM / FIFO
銆傜湡姝ｇ殑闆欑鍙AM妯″
銆傚寮风殑鍙伕鍙法绋婩IFO閭忚集
銆傚彲绶ㄧ▼鐨�
銆傜湡姝ｇ殑闆欑鍙ｅ搴﹀彲閬攛36
銆傜啊鍠殑闆欑鍙ｅ搴﹀彲閬攛72
銆傚収(n猫i)缃彲閬哥殑绯鹃尟闆昏矾
?锛熻泧x鎿囧皣姣忓�嬪绶ㄧ▼鐐哄叐鍊嬬崹绔嬬殑18-Kbit濉�
楂樻�ц兘骞惰SelectIO鎶�琛�(sh霉)
銆�1.2鑷�3.3VI / O鎿嶄綔
銆備娇鐢–hipSync?鎶�琛�(sh霉)閫茶婧愬悓姝ユ帴鍙�
銆傛暩(sh霉)瀛楁帶鍒堕樆鎶�(DCI)鏈夋簮绲傜
銆傞潏娲荤殑绱扮矑搴 / O閵�琛屾キ(y猫)鍕�(w霉)
銆傞珮閫熷収(n猫i)瀛樻帴鍙ｆ敮鎸�
鍏堥�茬殑DSP48E鍒囩墖
銆�25 x 18锛屼簩閫插埗瑁滅⒓锛屼箻娉�
?锛熻泧x鐨勫姞娉曞櫒锛屾笡娉曞櫒鍜岀疮鍔犲櫒
?锛熻泧x鐨勬祦姘寸窔
銆傚彲閬哥殑鎸変綅閭忚集鍔熻兘
銆傚皥鐢ㄧ礆鑱�(li谩n)閫ｆ帴
闈堟椿鐨勯厤缃伕闋�
銆係PI鍜屽苟琛孎LASH鎺ュ彛
銆傚叿鏈夊皥鐢ㄥ洖閫�閲嶉厤缃倧杓殑澶氭瘮鐗规祦鏀寔
銆傝嚜鍕曠附绶氬搴︽娓姛鑳�
鎵�鏈夎ō(sh猫)鍌欎笂鐨勭郴绲�(t菕ng)鐩�(ji膩n)鎺у姛鑳�
銆傜墖涓�/鐗囧鐔辩洠(ji膩n)鎺�
銆傜墖涓�/鐗囧闆绘簮鐩�(ji膩n)鎺�
銆侸TAG瑷晱鎵�鏈夊彈鐩�(ji膩n)鎺х殑鏁�(sh霉)閲�
鐢ㄤ簬PCI Express瑷�(sh猫)瑷堢殑闆嗘垚绔粸妯″
銆侺XT锛孲XT锛孴XT鍜孎XT骞宠嚭
銆傜鍚圥CI Express Base Specification 1.1
銆傛瘡鍊嬪x1锛寈4鎴杧8閫氶亾鏀寔
銆傝垏RocketIO?鏀剁櫦(f膩)鍣ㄩ厤鍚堜娇鐢�
涓夋ā10/100/1000 Mb / s浠ュお缍�(w菐ng)MAC
銆侺XT锛孲XT锛孴XT鍜孎XT骞宠嚭
銆俁ocketIO鏀剁櫦(f膩)鍣ㄥ彲鐢ㄤ綔PHY鎴栦娇鐢ㄨū澶氳粺MII(濯掗珨鐛ㄧ珛鎺ュ彛)閬搁爡閫ｆ帴鍒板閮≒HY
RocketIO GTP鏀剁櫦(f膩)鍣�100 Mb / s鑷�3.75 Gb / s
銆侺XT鍜孲XT骞宠嚭
RocketIO GTX鏀剁櫦(f膩)鍣ㄩ�熷害鐐�150 Mb / s鑷�6.5 Gb / s
銆俆XT鍜孎XT骞宠嚭
PowerPC 440寰檿鐞嗗櫒
銆傚儏闄怓XT骞宠嚭
銆俁ISC鏋舵(g貌u)
銆�7闅庢绠￠亾
銆傚寘鎷�32 KB鐨勬寚浠ゅ拰鏁�(sh霉)鎿�(j霉)绶╁瓨
銆傚劒(y艒u)鍖栫殑铏曠悊鍣ㄦ帴鍙ｇ祼(ji茅)妲�(g貌u)(crossbar)
65绱嶇背閵匔MOS宸ヨ棟鎶�琛�(sh霉)
1.0V鏍稿績闆诲
楂樹俊铏熷畬鏁存�у�掕鑺墖灏佽锛屾彁渚涙婧栨垨鐒￠墰灏佽閬搁爡
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎REACH妯欐簴 | 鏄� |
绗﹀悎姝愮洘RoHS妯欐簴 | 鏄� |
鐙�鎱�(t脿i) | 娲绘�� |
鏅傞悩闋荤巼-鏈�澶у�� | 1265.0 MHz |
JESD-30浠ｇ⒓ | S-PBGA-B324 |
JESD-609浠ｇ⒓ | E1 |
绺絉AM浣嶆暩(sh霉) | 1179648 |
CLB鏁�(sh霉)閲� | 2400.0 |
杓稿叆鏁�(sh霉)閲� | 220.0 |
閭忚集鍠厓鐨勬暩(sh霉)閲� | 30720.0 |
杓稿嚭鏁�(sh霉)閲� | 220.0 |
绲傜鏁�(sh霉)閲� | 324 |
绲勭箶 | 2400 CLBS |
宄板�煎洖娴佹韩搴�(鈩�) | 250 |
闆绘簮 | 1,2.5 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
鍧愬Э楂樺害-鏈�澶� | 2.85姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲 | 1.0 V |
闆绘簮闆诲-鏈�灏忓�� | 0.95 V |
闆绘簮闆诲-鏈�澶у�� | 1.05 V |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
绲傜瀹屾垚 | 閷�/閵�/閵�(Sn95.5Ag4.0Cu0.5) |
绲傜琛ㄦ牸 | 鐞� |
绲傜闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶у��(s) | 涓夊崄 |
闀峰害 | 19.0姣背 |
瀵害 | 19.0姣背 |
鍖呰楂旀潗鏂� | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰９浠ｇ⒓ | BGA |
鍖呯瓑鍍逛唬纰� | BGA324,18X18,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰棰�(f膿ng)鏍� | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 19 X 19 MM锛岀劇閴�锛孎(xi脿n)BGA-324 |
IC鍨嬭櫉绱㈠紩锛� A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0 1 2 3 4 5 6 7 8 9
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