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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XC5VLX220-2FFG1760C

XC5VLX220-2FFG1760C 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2023/7/18 17:57:18 鏌ョ湅 闁辫畝锛�222

鎻忚堪

XC5VLX220-2FFG1760C閲囩敤绗簩浠SMBLTM(楂樼礆纭呯墖绲勫悎妯″)鍒楀紡鏋舵(g貌u)锛屽寘鍚洓绋埅鐒朵笉鍚岀殑骞宠嚭(瀛愮郴鍒�)锛屾瘮姝ゅ墠浠讳綍FPGA绯诲垪鎻愪緵鐨勯伕鎿囪寖鍦嶉兘澶�銆傛瘡绋钩鑷洪兘鍖呭惈涓嶅悓鐨勫姛鑳介厤姣�锛屼互婊胯冻璜稿楂樼礆閭忚集瑷�(sh猫)瑷堢殑闇�姹�銆傛湰姒傝堪鍖呭惈闂�(gu膩n)浜嶭X銆丩XT鍜孲XT骞宠嚭鐨勮┏绱�(x矛)淇℃伅銆傞櫎浜嗗緢鍏堥��(j矛n)鐨勬�ц兘閭忚集鏋舵(g貌u)锛岄倓鍖呭惈澶氱ó纭琁P绯荤当(t菕ng)绱氭ā濉婏紝鍖呮嫭寮�(qi谩ng)澶х殑36Kb Block RAM/FIFO銆佺浜屼唬25x 18 DSP Slice銆佸付鏈夊収(n猫i)缃暩(sh霉)鎺ч樆鎶楃殑SelectlOTM鎶�琛�(sh霉)銆丆hipSyncTM 婧愬悓姝ユ帴鍙ｆā濉�銆佺郴绲�(t菕ng)鐩�(ji膩n)瑕栧櫒鍔熻兘銆佸付鏈夐泦鎴怐CM ( 鏁�(sh霉)瀛楁檪閻樼鐞嗗櫒)鍜岄帠鐩哥挵(hu谩n)(PLL)鏅傞悩銆傜櫦(f膩)鐢熷櫒鐨勫寮�(qi谩ng)鍨嬫檪閻樼鐞嗘ā濉婁互鍙婇珮绱氶厤缃伕闋呫�侺XT鍜孲XT鍣ㄤ欢閭勫寘鍚嚌灏嶅寮�(qi谩ng)鍨嬩覆琛岄�ｆ帴鐨勯浕婧愬劒(y艒u)鍖栭珮閫熻睈琛屾敹鐧�(f膩)鍣ㄦā濉�銆佷竴鍊嬬鍚圥CI ExpressTM鐨勯泦鎴愮榛�(di菐n)妯″鍜屼笁鎱�(t脿i)浠ュお缍�(w菐ng)MAC ( 濯掗珨瑷晱鎺у埗鍣�)銆傞�欎簺鍔熻兘浣块珮绱氶倧杓ō(sh猫)瑷堜汉鍝¤兘澶犲湪鍏跺熀浜嶧PGA鐨勭郴绲�(t菕ng)涓珨鐝�(xi脿n)鏈�楂樻獢娆＄殑鎬ц兘鍜屽姛鑳姐��

鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸瀷铏�

XC5VLX220-2FFG1760C

鎻忚堪

闆嗘垚闆昏矾FPGA 800 I / O 1760FCBGA

鍒嗛

闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪)

鍒堕�犲晢

Xilinx鍏徃

绯诲垪

Virtex?-5LX

鎵撳寘

鎵樼洡

闆诲-闆绘簮

0.95V?1.05V

宸ヤ綔婧害

0掳C?85掳C(TJ)

鍖呰/绠�

1760-BBGA锛孎(xi脿n)CBGA

渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�

1760-FCBGA(42.5x42.5)

鍩烘湰闆朵欢铏�

XC5VLX220

鐢�(ch菐n)鍝佸湒鐗�

XC5VLX220-2FFG1760C

XC5VLX220-2FFG1760C

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍒堕�犲晢鍖呰瑾槑

42.50 X 42.50 MM锛岀劇閴涳紝F(xi脿n)BGA-1760

绗﹀悎REACH

鏄�

绗﹀悎姝愮洘RoHS

鏄�

鐙�鎱�(t脿i)

娲绘��

鍙法绋嬮倧杓鍨�

鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪

鏈�澶ф檪閻橀牷鐜�

1265.0鍏嗚但

JESD-30浠ｇ⒓

S-PBGA-B1760

JESD-609浠ｇ⒓

e1

绺絉AM浣�

7077888

CLB鏁�(sh霉)閲�

17280.0

杓稿叆鏁�(sh霉)閲�

800.0

閭忚集鍠厓鏁�(sh霉)

221184.0

杓稿嚭鏁�(sh霉)閲�

800.0

绔瓙鏁�(sh霉)

1760

鏈�浣庡伐浣滄韩搴�

0鈩�

鏈�楂樺伐浣滄韩搴�

85鈩�

绲勭箶

17280 CLBS

鍖呰涓婚珨鏉愭枡

濉戞枡/鐠�(hu谩n)姘фü鑴�

鍖呰浠ｇ⒓

BGA

鍖呰绛夋晥浠ｇ⒓

BGA1760,42X42,40

鍖呰褰㈢媭

鍥涙柟褰�

鍖呰褰㈠紡

缍�(w菐ng)鏍奸櫍鍒�

宄板�煎洖娴佹韩搴�(鈩�)

245

闆绘簮

1,2.5

搴ч珮

3.5姣背

瀛愰鍒�

鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪

闆绘簮闆诲妯�(bi膩o)绋�

1.0浼�

鏈�灏忎緵闆婚浕澹�

0.95浼�

鏈�澶ч浕婧愰浕澹�

1.05浼�

瀹夎椤炲瀷

琛ㄩ潰璨艰

鎶�琛�(sh霉)

CMOS

婧害绛夌礆

鍏朵粬

绲傜瀹屾垚

閷�/閵�/閵�(Sn95.5Ag4.0Cu0.5)

绲傜琛ㄦ牸

鐞�

绔瓙闁撹窛

1.0姣背

绲傜浣嶇疆

搴曢儴

鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶у��(绉�)

30

闀峰害

42.5姣背

瀵害

42.5姣背

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

RoHS鐙�鎱�(t脿i)

绗﹀悎ROHS3

姘村垎鏁忔劅鎬ф按骞�(MSL)

4(72灏忔檪)

CAD妯″瀷

XC5VLX220-2FFG1760C绗﹁櫉

XC5VLX220-2FFG1760C绗﹁櫉

XC5VLX220-2FFG1760C鑵冲嵃

XC5VLX220-2FFG1760C鑵冲嵃

灏佽

XC5VLX220-2FFG1760C灏佽

XC5VLX220-2FFG1760C灏佽

鏇夸唬鍨嬭櫉

鍨嬭櫉

鍒堕�犲晢

鍝佸悕

鎻忚堪

XC5VLX220-1FFG1760C

璩介潏鎬�

FPGA鑺墖

221184 Cells 65nm (CMOS) Technology 1V 1760Pin FCBGA

XC5VLX220-1FF1760C

璩介潏鎬�

FPGA鑺墖

17280 CLBs 1098MHz 221184-Cell CMOS PBGA

XC5VLX220-2FFG1760I

璩介潏鎬�

FPGA鑺墖

221184 Cells 65nm (CMOS) Technology 1V 1760Pin FCBGA

xc5vlx220-2ffg1760c鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xc5vlx220-2ffg1760c鍦栫墖

xc5vlx220-2ffg1760c

xc5vlx220-2ffg1760c鐢�(ch菐n)鍝�

xc5vlx220-2ffg1760c鍙冩暩(sh霉)

  • 妯�(bi膩o)婧�(zh菙n)鍖呰1
  • 椤炲垾闆嗘垚闆昏矾 (IC)
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  • LAB/CLB鏁�(sh霉)17280
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)221184
  • RAM 浣嶇附瑷�7077888
  • 杓稿叆/杓稿嚭鏁�(sh霉)800
  • 闁�鏁�(sh霉)-
  • 闆绘簮闆诲0.95 V ~ 1.05 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害0°C ~ 85°C
  • 灏佽/澶栨1760-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�1760-FCBGA
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