XC5VLX20T-2FFG323C 鏅傞枔锛�2022/10/20 14:00:44 闁辫畝锛�1021

鐢�(ch菐n)鍝佸瀷铏�	XC5VLX20T-2FFG323C
鎻忚堪	闆嗘垚闆昏矾FPGA 172 I / O 323FCBGA
椤炲垾	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)

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鐢�(ch菐n)鍝佸瀷铏�	XC5VLX20T-2FFG323C
鎻忚堪	闆嗘垚闆昏矾FPGA 172 I / O 323FCBGA
椤炲垾	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鍒堕€犲晢	Xilinx鍏徃
绯诲垪	Virtex?-5LXT
鎵撳寘	鎵樼洡
闆诲-闆绘簮	0.95V1.05V
宸ヤ綔婧害	0掳C85掳C(TJ)
鍖呰/绠�	323-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	323-FCBGA(19x19)
鍩烘湰闆朵欢铏�	XC5VLX20T

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鏀归€茬殑娓涘皯韬嶉粸璺敱

64浣嶅垎甯冨紡RAM閬搁爡

SRL32/Dual SRL16閬搁爡

寮峰ぇ鐨勬檪閻樼鐞嗙璨�(CMT)鏅傞悩

鏁�(sh霉)瀛楁檪閻樼鐞嗗櫒(DCM)妯″鐢ㄤ簬闆跺欢閬茬珐娌�锛岄牷鐜囧悎鎴愬拰鏅傞悩鐩哥Щ

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澧炲挤鐨勫彲閬稿彲绶ㄧ▼FIFO閭忚集

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LXT鍜孲XT骞宠嚭

65绱嶇背閵匔MOS宸ヨ棟鎶€琛�(sh霉)

1.0V鏍稿績闆诲

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鍙冩暩(sh霉)

鍒堕€犲晢鍖呰瑾槑	19 X 19 MM锛岀劇閴�锛孎(xi脿n)BGA-323
绗﹀悎姝愮洘RoHS	鏄�
鐙€鎱�(t脿i)	娲绘€�
鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
鏈€澶ф檪閻橀牷鐜�	1265.0鍏嗚但
JESD-30浠ｇ⒓	S-PBGA-B323
JESD-609浠ｇ⒓	e1
绺絉AM浣�	958464
CLB鏁�(sh霉)閲�	1560.0
杓稿叆鏁�(sh霉)閲�	172.0
绔瓙鏁�(sh霉)	323
鏈€浣庡伐浣滄韩搴�	0鈩�
鏈€楂樺伐浣滄韩搴�	85鈩�
绲勭箶	1560 CLBS
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA323,18X18,40
鍖呰褰㈢媭	鍥涙柟褰�
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
宄板€煎洖娴佹韩搴�(鈩�)	250
闆绘簮	1,2.5
搴ч珮	2.85姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	1.0浼�
鏈€灏忎緵闆婚浕澹�	0.95浼�
鏈€澶ч浕婧愰浕澹�	1.05浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆	鍏朵粬
绲傜瀹屾垚	閷�/閵€/閵�(Sn95.5Ag4.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅傞枔@宄板€煎洖娴佹韩搴�-鏈€澶у€�(绉�)	30
闀峰害	19.0姣背
瀵害	19.0姣背