鏅傞枔锛�2023/8/3 17:58:53
闁辫畝锛�505
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鐢�(ch菐n)鍝佸瀷铏� | XC5VLX155-2FFG1153I |
鎻忚堪 | 闆嗘垚闆昏矾FPGA 800 I/O 1153FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢熺敘(ch菐n)寤犲 | Xilinx鍏徃 |
绯诲垪 | Virtex?-5LX |
闆朵欢鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 0.95V?1.05V |
宸ヤ綔婧害 | -40掳C?100掳C(TJ) |
鍖呰/绠� | 1153-BBGA锛孎(xi脿n)CBGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁� | 1153-FCBGA(35x35) |
鍩烘湰闆朵欢铏� | XC5VLX155 |
XC5VLX155-2FFG1153I
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎REACH | 鏄� |
绗﹀悎姝愮洘RoHS | 鏄� |
鐙�鎱�(t脿i) | 娲绘�� |
鏈�澶ф檪閻橀牷鐜� | 1265.0鍏嗚但 |
JESD-30浠ｇ⒓ | S-PBGA-B1153 |
JESD-609浠ｇ⒓ | E1 |
绺絉AM浣� | 7077888 |
CLB鏁�(sh霉)閲� | 12160.0 |
杓稿叆鏁�(sh霉)閲� | 800.0 |
閭忚集鍠厓鏁�(sh霉) | 155648.0 |
杓稿嚭鏁�(sh霉)閲� | 800.0 |
绔瓙鏁�(sh霉) | 1153 |
绲勭箶 | 12160 CLBS |
宄板�煎洖娴佹韩搴�(鈩�) | 245 |
闆绘簮 | 1,2.5 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
搴ч珮 | 3.4姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲妯�(bi膩o)绋� | 1.0浼� |
鏈�灏忎緵闆婚浕澹� | 0.95浼� |
鏈�澶ч浕婧愰浕澹� | 1.05浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
绲傜瀹屾垚 | 閷�/閵�/閵�(Sn95.5Ag4.0Cu0.5) |
绲傜琛ㄦ牸 | 鐞� |
绔瓙闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴︽渶澶у��(绉�) | 涓夊崄 |
闀峰害 | 35.0姣背 |
瀵害 | 35.0姣背 |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呰绛夋晥浠ｇ⒓ | BGA1153,34X34,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰褰㈠紡 | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 35 X 35 MM锛岀劇閴�锛孎(xi脿n)BGA-1153 |
| 灞�� | 鎻忚堪 |
鐒￠墰鐙�鎱�(t脿i)/RoHS鐙�鎱�(t脿i) | 鐒￠墰/绗﹀悎ROHS3 |
婵曞害鏁忔劅搴︾瓑绱�(MSL) | 4(72灏忔檪) |
?浜斿�嬪钩鑷篖X锛孡XT锛孲XT锛孴XT鍜孎XT
銆俈irtex-5 LX锛氶珮鎬ц兘閫氱敤閭忚集鎳�(y墨ng)鐢�
銆俈irtex-5 LXT锛氬叿鏈夐珮绱氫覆琛岄�ｆ帴鐨勯珮鎬ц兘閭忚集
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銆俈irtex-5 TXT锛氬叿鏈夐洐瀵嗗害楂樼礆涓茶閫ｆ帴鐨勯珮鎬ц兘绯荤当(t菕ng)
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?36 Kb濉奟AM / FIFO
銆傜湡姝ｇ殑闆欑鍙AM濉�
銆傚寮风殑鍙伕鍙法绋婩IFO閭忚集
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銆傜啊鍠殑闆欑鍙ｅ搴﹂珮閬攛72
銆傚収(n猫i)缃彲閬哥殑绯鹃尟闆昏矾
銆�(鍙伕)灏囨瘡鍊嬪绶ㄧ▼鐐哄叐鍊嬬崹绔嬬殑18-Kbit濉�
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銆�1.2鑷�3.3VI / O鎿嶄綔
銆備娇鐢–hipSync?鎶�琛�(sh霉)鐨勬簮鍚屾鎺ュ彛
銆傛暩(sh霉)鎺ч樆鎶�(DCI)鏈夋簮绲傜
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銆傞珮閫熷瓨鍎插櫒鎺ュ彛鏀寔
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銆�25 x 18锛屼簩閫插埗瑁滅⒓锛屼箻娉�
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銆傜鍚圥CI Express鍩烘湰瑕�(gu墨)鑼�1.1
銆傛瘡濉妜1锛寈4鎴杧8閫氶亾鏀寔
銆傝垏RocketIO?鏀剁櫦(f膩)鍣ㄩ厤鍚堜娇鐢�
?涓夋ā10/100/1000 Mb / s浠ュお缍�(w菐ng)MAC
銆侺XT锛孲XT锛孴XT鍜孎XT骞宠嚭
銆俁ocketIO鏀剁櫦(f膩)鍣ㄥ彲浠ョ敤浣淧HY鎴栦娇鐢ㄨū澶氳粺MII(濯掗珨鐛ㄧ珛鎺ュ彛)閬搁爡閫ｆ帴鍒板閮≒HY
?RocketIO GTP鏀剁櫦(f膩)鍣�100 Mb / s鑷�3.75 Gb / s
銆侺XT鍜孲XT骞宠嚭
?RocketIO GTX鏀剁櫦(f膩)鍣�150 Mb / s鑷�6.5 Gb / s
銆俆XT鍜孎XT骞宠嚭
?PowerPC 440寰檿鐞嗗櫒
銆傚儏FXT骞宠嚭
銆俁ISC鏋舵(g貌u)
銆�7绱氭祦姘寸窔
銆傚寘鎷�32 KB鐨勬寚浠ゅ拰鏁�(sh霉)鎿�(j霉)绶╁瓨
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XC5VLX155-2FFG1153I绗﹁櫉
XC5VLX155-2FFG1153I鑵冲嵃
XC5VLX155-2FFG1153I灏佽
鍨嬭櫉 | 鍒堕�犲晢 | 鍝佸悕 | 鎻忚堪 |
XC5VLX155-1FFG1153C | 璩介潏鎬� | FPGA鑺墖 | 65nm Technology 1V 1153Pin FCBGA |
XC5VLX155-1FFG1153I | 璩介潏鎬� | FPGA鑺墖 | 65nm Technology 1V 1153Pin FCBGA |
XC5VLX155-2FFG1153C | 璩介潏鎬� | FPGA鑺墖 | 65nm Technology 1V 1153Pin FCBGA |
IC鍨嬭櫉绱㈠紩锛� A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0 1 2 3 4 5 6 7 8 9
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