鏅傞枔锛�2025/5/26 16:21:33
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XC5VLX155-2FF1153I鏄疿ilinx鍏徃鎺ㄥ嚭鐨刅irtex-5绯诲垪FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛夎姱鐗囦腑鐨勪竴鍊嬪瀷铏�銆傝┎绯诲垪FPGA鍩轰簬65nm宸ヨ棟鎶�琛�锛屾彁渚涗簡楂樻�ц兘鍜岄珮瀵嗗害鐨勯倧杓硣婧�锛岄仼鐢ㄤ簬闇�瑕佸京闆滅畻娉曡檿鐞嗐�侀珮閫熶俊铏熷偝杓镐互鍙婂鎺ュ彛鏀寔鐨勬噳鐢ㄥ牬鏅�銆�
銆�銆�Virtex-5绯诲垪鍒嗙偤澶氬�嬪瓙绯诲垪锛孹C5VLX155灞簬LX瀛愮郴鍒楋紝涓昏闈㈠悜楂橀倧杓瘑搴﹀拰DSP鍔熻兘闇�姹傜殑瑷▓銆傛鍨嬭櫉鍏锋湁璞愬瘜鐨勫収閮ㄨ硣婧�锛屽寘鎷彲绶ㄧ▼閭忚集鍠厓銆佸祵鍏ュ紡瀛樺劜鍣ㄥ銆丏SP slice绛夛紝骞舵敮鎸佸绋珮閫熶覆琛屾帴鍙�銆�
鍣ㄤ欢椤炲瀷锛欶PGA
銆�銆�绯诲垪锛歏irtex-5 LX
銆�銆�鍨嬭櫉锛歑C5VLX155
銆�銆�閫熷害绛夌礆锛�-2
銆�銆�灏佽锛欶F1153
銆�銆�I/O寮曡叧鏁�(sh霉)锛�940
銆�銆�閰嶇疆闁冨瓨锛氫笉鍏х疆
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細155,000
銆�銆�鏈�澶х敤鎴禝/O锛�768
銆�銆�鐗囦笂RAM瀹归噺锛�11.2Mb
銆�銆�DSP Slice鏁�(sh霉)閲忥細768
銆�銆�閰嶇疆妯″紡锛歋lave Serial / Master SelectMAP / Boundary Scan
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銆�銆�1. 楂樻�ц兘閭忚集绲愭锛氭敮鎸侀珮閬�500MHz浠ヤ笂鐨勭郴绲�(t菕ng)鏅傞悩闋荤巼锛岄仼鍚堥珮閫熸暩(sh霉)鎿�(j霉)铏曠悊浠诲嫏銆�
銆�銆�2. 璞愬瘜鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗚兘鍔涳細闆嗘垚768鍊婦SP slices锛屾瘡鍊媠lice鍙互鍩�(zh铆)琛屼箻娉曠疮鍔犻亱绠�锛岄潪甯搁仼鍚堟烤娉㈠櫒瑷▓鍜屽叾浠栨暩(sh霉)瀛稿瘑闆嗗瀷绠楁硶銆�
銆�銆�3. 宓屽叆寮忓瓨鍎插櫒锛氭彁渚涘閬�11.2Mb鐨凚lock RAM璩囨簮锛屽彲鐢ㄤ簬瀵︾従(xi脿n)FIFO銆佹煡鎵捐〃绛夊姛鑳�銆�
銆�銆�4. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細鏀寔鏈�楂�6.5Gbps鐨勪覆琛岄�ｆ帴閫熺巼锛屽吋瀹瑰绋�氫俊鍗�(xi茅)璀板PCIe銆丼ATA銆丟bE绛�銆�
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銆�銆�6. 浣庡姛鑰楁ā寮忥細鍙�氶亷鍕曟厠(t脿i)闆诲瑾跨瘈(ji茅)鎶�琛撻檷浣庡伐浣滈浕娴�锛屽欢闀烽浕姹犲＝鍛芥垨娓涘皯鏁ｇ啽闇�姹傘��
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瑭插瀷铏熺殑FPGA寤ｆ硾鎳夌敤浜庨�氫俊銆佽埅绌鸿埅澶�銆侀啱(y墨)鐧傛垚鍍�銆佽闋昏檿鐞嗗強宸ユキ(y猫)鑷嫊鍖栫瓑闋樺煙銆�
銆�銆�1. 閫氫俊瑷倷锛�
銆�銆� - 鍩虹珯铏曠悊鍣�
銆�銆� - 璺敱鍣�/浜ゆ彌姗熺殑鏍稿績鎺у埗鍠厓
銆�銆�2. 鍦栧儚铏曠悊锛�
銆�銆� - 閱�(y墨)鐧傚奖鍍忓垎鏋愬剙
銆�銆� - 楂樺垎杈ㄧ巼瑕栭牷绶ㄨВ纰煎櫒
銆�銆�3. 娓│娓噺锛�
銆�銆� - 瀵︽檪淇¤櫉鐧�(f膩)鐢熷櫒
銆�銆� - 绀烘尝鍣ㄥ墠绔暩(sh霉)鎿�(j霉)閲囬泦妯″
銆�銆�4. 宸ユキ(y猫)鎺у埗锛�
銆�銆� - 澶氳桓閬嬪嫊鎺у埗鍣�
銆�銆� - 瀹夊叏鐩�(ji膩n)鎺х郴绲�(t菕ng)
銆�銆�姝ゅ锛岀敱浜庡叾楂樺害鍙畾鍒跺寲鐗归粸锛岄倓琚敤浜庨枊鐧�(f膩)灏堢敤闆嗘垚闆昏矾(ASIC)鍘熷瀷椹楄瓑骞宠嚭銆�
XC5VLX110T-2FF1136I
銆�銆�XC5VLX330T-2FF1737I
