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鎮ㄥソ锛屾杩庝締(l谩i)鍒扮董搴�(k霉)闆诲瓙甯傚牬(ch菐ng)缍�(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺(c猫)

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩�(g貌u)缍�(w菐ng) > IC鐧剧 > XC5VLX155-1FFG1760C

XC5VLX155-1FFG1760C 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2025/4/30 16:52:49 鏌ョ湅 闁辫畝锛�27

XC5VLX155-1FFG1760C鏄疿ilinx鍏徃鎺ㄥ嚭鐨刅irtex-5绯诲垪FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪锛夌敘(ch菐n)鍝佷腑鐨勪竴鍊�(g猫)鍨嬭櫉(h脿o)銆傝┎绯诲垪鍣ㄤ欢鍩轰簬鍏堥��(j矛n)鐨�65nm宸ヨ棟鍒堕��锛屽叿鏈夐珮閭忚集瀵嗗害銆佽睈瀵岀殑宓屽叆寮忓瓨鍎�(ch菙)鍣ㄥ拰DSP Slice璩囨簮锛岄仼鍚堢敤浜庨珮鎬ц兘瑷�(j矛)绠�銆侀�氫俊绯荤当(t菕ng)銆佸湒鍍忚檿鐞�銆佸伐妤�(y猫)鎺у埗绛夊京(f霉)闆滄噳(y墨ng)鐢ㄩ牁(l菒ng)鍩�銆�
銆�銆�Virtex-5 FPGA绯诲垪鍒嗙偤澶氬��(g猫)瀛愮郴鍒�锛屽叾涓璍X锛圠ogic Extreme锛夊瓙绯诲垪灏堟敞浜庨珮鎬ц兘閭忚集鍔熻兘锛岄仼鐢ㄤ簬闇�瑕佸ぇ瑕�(gu墨)妯℃暩(sh霉)瀛椾俊铏�(h脿o)铏曠悊鍜屽京(f霉)闆滈倧杓ō(sh猫)瑷�(j矛)鐨勬噳(y墨ng)鐢ㄥ牬(ch菐ng)鏅�銆俋C5VLX155鏄疞X瀛愮郴鍒椾腑鐨勪竴鍝�锛屾彁渚涘閬�(d谩)155K閭忚集鍠厓锛岃兘澶犳敮鎸佸京(f霉)闆滅殑绠楁硶瀵�(sh铆)鐝�(xi脿n)鍜屾暩(sh霉)鎿�(j霉)璺緫瑷�(sh猫)瑷�(j矛)銆�

鍙冩暩(sh霉)

鍨嬭櫉(h脿o)锛歑C5VLX155-1FFG1760C
銆�銆�绯诲垪锛歏irtex-5 LX
銆�銆�宸ヨ棟绡�(ji茅)榛�(di菐n)锛�65nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細155K
銆�銆�閰嶇疆闁冨瓨锛氱劇(w煤)鍏�(n猫i)缃杻瀛橈紝闇�澶栭儴閰嶇疆鑺墖
銆�銆�宸ヤ綔闆诲锛�1.0V鏍稿績闆诲锛�2.5V/3.3V I/O闆诲
銆�銆�灏佽褰㈠紡锛欶FG1760锛�1760寮曡叧Fine Pitch BGA锛�
銆�銆�閫熷害绛夌礆(j铆)锛�-1
銆�銆�瀛樺劜(ch菙)鍣ㄨ硣婧愶細绱�9MB Block RAM锛�360鍊�(g猫)18Kb BRAM濉�
銆�銆�DSP Slice鏁�(sh霉)閲忥細320鍊�(g猫)
銆�銆�鏈�澶х敤鎴禝/O锛�1049
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丮aster/Slave SPI銆丅PI銆丅oundary Scan

鐗规��

XC5VLX155-1FFG1760C鍏峰倷浠ヤ笅涓昏鐗规�э細
銆�銆�1. 楂樻�ц兘鏋舵(g貌u)锛氶噰鐢╔ilinx绗簩浠SMBL锛圓dvanced Site-based Meta Block Logic锛夋灦妲�(g貌u)锛屾敮鎸侀珮閬�(d谩)550 MHz鐨勬檪(sh铆)閻橀牷鐜�銆�
銆�銆�2. 宓屽叆寮忓瓨鍎�(ch菙)鍣細鎻愪緵澶ч噺鐨凚lock RAM璩囨簮锛屽彲鐢ㄤ簬瀵�(sh铆)鐝�(xi脿n)FIFO銆佺珐瀛樹互鍙婂叾浠栧瓨鍎�(ch菙)闇�姹�銆�
銆�銆�3. DSP Slice鏀寔锛氭瘡鍊�(g猫)DSP Slice鍖呭惈鍏╁��(g猫)18脳18涔樻硶鍣ㄥ拰涓�鍊�(g猫)48浣嶅姞娉曞櫒/绱姞鍣�锛岄潪甯搁仼鍚堟暩(sh霉)瀛椾俊铏�(h脿o)铏曠悊浠诲嫏(w霉)銆�
銆�銆�4. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細闆栫劧LX瀛愮郴鍒椾笉鍖呭惈闆嗘垚鐨勯珮閫熶覆琛屾敹鐧�(f膩)鍣�锛屼絾鍙互閫氶亷(gu貌)纭畯鎴栬粺鏍稿(sh铆)鐝�(xi脿n)澶氱ó鎺ュ彛鍗�(xi茅)璀般��
銆�銆�5. 鏀寔澶氱ó閰嶇疆妯″紡锛氬厑瑷遍潏娲婚伕鎿囬厤缃柟寮忎互閬╅厤涓嶅悓鎳�(y墨ng)鐢ㄥ牬(ch菐ng)鏅�銆�
銆�銆�6. 澶ц(gu墨)妯￠倧杓閲忥細155K閭忚集鍠厓瓒充互婊胯冻澶у鏁�(sh霉)楂樼鏁�(sh霉)瀛楅浕璺ō(sh猫)瑷�(j矛)闇�姹�銆�
銆�銆�7. 宸ヨ棟鍎�(y艒u)鍕�(sh矛)锛�65nm宸ヨ棟涓嶅儏闄嶄綆浜嗗姛鑰�锛岄倓鎻愬崌浜嗘�ц兘鍜岄泦鎴愬害銆�
銆�銆�8. 寤ｆ硾鐨処/O妯�(bi膩o)婧�(zh菙n)鍏煎鎬э細鏀寔澶氱ó甯哥敤I/O妯�(bi膩o)婧�(zh菙n)锛屽LVDS銆丠STL銆丼STL绛�锛屼究浜庤垏澶栭儴瑷�(sh猫)鍌欓�ｆ帴銆�

鎳�(y墨ng)鐢�

XC5VLX155-1FFG1760C寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 閫氫俊瑷�(sh猫)鍌欙細濡傚熀绔�銆佽矾鐢卞櫒銆佷氦鎻涙(j墨)绛�锛岀敤浜庡(sh铆)鐝�(xi脿n)寰�(f霉)闆滅殑淇¤櫉(h脿o)铏曠悊鍜屽崝(xi茅)璀拌綁(zhu菐n)鎻涖��
銆�銆�2. 鍦栧儚鑸囪闋昏檿鐞嗭細渚嬪楂樻竻瑕栭牷绶ㄧ⒓瑙ｇ⒓鍣�銆佸湒褰㈠姞閫熷櫒绛�銆�
銆�銆�3. 鏁�(sh霉)鎿�(j霉)涓績锛氱敤浣滃崝(xi茅)铏曠悊鍣ㄤ互鍔犻�熺壒瀹氶鍨嬬殑鏁�(sh霉)鎿�(j霉)閬�(y霉n)绠椼��
銆�銆�4. 閱�(y墨)鐧傝ō(sh猫)鍌欙細濡傝秴鑱叉尝鎴愬儚銆丆T鎺冩弿鍎�绛夐啱(y墨)鐧傚奖鍍忚ō(sh猫)鍌欎腑鐨勪俊铏�(h脿o)铏曠悊妯″銆�
銆�銆�5. 宸ユキ(y猫)鑷嫊(d貌ng)鍖栵細閬�(y霉n)鍕�(d貌ng)鎺у埗鍣�銆佹(j墨)鍣ㄤ汉瑕栬(ju茅)绯荤当(t菕ng)绛�銆�
銆�銆�6. 杌嶄簨鑸囪埅绌鸿埅澶╋細闆烽仈(d谩)绯荤当(t菕ng)銆佽(w猫i)鏄熼�氫俊绛夊皪(du矛)鍙潬鎬ц姹傛サ楂樼殑鍫�(ch菐ng)鍚�銆�
銆�銆�鐢变簬鍏跺挤(qi谩ng)澶х殑閭忚集铏曠悊鑳藉姏鍜岃睈瀵岀殑纭欢璩囨簮锛岄�欐FPGA骞句箮鍙互瑕嗚搵浠讳綍闇�瑕侀珮搴﹀畾鍒跺寲纭欢鍔犻�熺殑鎳�(y墨ng)鐢ㄥ牬(ch菐ng)鏅��

鏇夸唬鍨嬭櫉(h脿o)

XC5VLX110T-1FFG1136C
銆�銆�XC5VLX330T-1FFG1760C

xc5vlx155-1ffg1760c鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�(h脿o)
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉(h脿o)
  • 瑭㈠児(ji脿)

xc5vlx155-1ffg1760c鍙冩暩(sh霉)

  • 妯�(bi膩o)婧�(zh菙n)鍖呰1
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪锛�
  • 绯诲垪Virtex®-5 LX
  • LAB/CLB鏁�(sh霉)12160
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)155648
  • RAM 浣嶇附瑷�(j矛)7077888
  • 杓稿叆/杓稿嚭鏁�(sh霉)800
  • 闁�(m茅n)鏁�(sh霉)-
  • 闆绘簮闆诲0.95 V ~ 1.05 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害0°C ~ 85°C
  • 灏佽/澶栨1760-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�1760-FCBGA
  • 閰嶇敤568-5088-ND - BOARD DEMO DAC1408D750HW-AFX-FF1760-500-G-ND - BOARD DEV VIRTEX 5 FF1760