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鍨嬭櫉锛歑C5VLX155-1FFG1153I
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銆€銆€鍒剁▼宸ヨ棟锛�65nm
銆€銆€FPGA鏋舵(g貌u)锛歋partan/LUT-based
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銆€銆€RAM瀹归噺锛�7.4Mb
銆€銆€DSP Slice鏁�(sh霉)閲忥細960鍊�
銆€銆€I/O寮曡叧鏁�(sh霉)閲忥細840鍊�
銆€銆€閰嶇疆妯″紡锛歋electMAP, JTAG
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