鏅傞枔锛�2023/8/4 17:45:09
闁辫畝锛�706
鐢�(ch菐n)鍝佸瀷铏� | XC5VLX155-1FFG1153C |
鎻忚堪 | IC FPGA 800 I/O 1153FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢熺敘(ch菐n)寤犲 | Xilinx鍏徃 |
绯诲垪 | Virtex?-5 LX |
閮ㄥ垎鐙�鎱�(t脿i) | 娲绘�� |
宸ヤ綔婧害 | 0掳C~85掳C(TJ) |
鍖�/绠� | 1153-BBGA锛孎(xi脿n)CBGA |
鍩虹閮ㄤ欢铏� | XC5VLX155 |
渚涙噳鍟嗚ō鍌欏寘 | 1153-FCBGA(35x35) |
XC5VLX155-1FFG1153C
| 鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
鐙�鎱�(t脿i) | 娲绘�� |
绗﹀悎姝愮洘RoHS妯欐簴 | 鏄� |
绗﹀悎REACH妯欐簴 | 鏄� |
鍒堕�犲晢鍖呰瑾槑 | 35 X 35 MM锛岀劇閴�锛孎(xi脿n)BGA-1153 |
鏅傞悩闋荤巼-鏈�澶у�� | 1098.0 MHz |
JESD-30浠ｇ⒓ | S-PBGA-B1153 |
JESD-609浠ｇ⒓ | E1 |
CLB鏁�(sh霉)閲� | 12160.0 |
杓稿叆鏁�(sh霉)閲� | 800.0 |
閭忚集鍠厓鐨勬暩(sh霉)閲� | 155648.0 |
杓稿嚭鏁�(sh霉)閲� | 800.0 |
绲傜鏁�(sh霉)閲� | 1153 |
宸ヤ綔婧害-鏈�灏忓�� | 0鈩冧笅 |
宸ヤ綔婧害-鏈�楂� | 85鈩� |
绲勭箶 | 12160 CLBS |
鍖呰楂旀潗鏂� | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰９浠ｇ⒓ | BGA |
鍖呯瓑鍍逛唬纰� | BGA1153,34X34,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰棰ㄦ牸 | 缍�(w菐ng)鏍奸櫍鍒� |
宄板�煎洖娴佹韩搴�(掳C) | 245 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
鍧愬Э楂樺害-鏈�澶� | 3.4姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
灏堢敤DSP | 128 |
Giga Multiply姣忕绱▓ | 70.4 |
閫熷害绛夌礆 | 1 |
Block RAM绺芥暩(sh霉) | 192 |
闆绘簮闆诲 | 1.0 V |
闆绘簮闆诲-鏈�灏忓�� | 0.95 V |
闆绘簮闆诲-鏈�澶у�� | 1.05 V |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛� | CMOS |
婧害绛夌礆 | 鍏朵粬 |
绋嬪簭瀛樺劜鍣ㄩ鍨� | SRAM |
绲傜瀹屾垚 | 閷�/閵�/閵�(Sn95.5Ag4.0Cu0.5) |
绲傜琛ㄦ牸 | 鐞� |
绲傜闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶у�� | 涓夊崄 |
闀峰害 | 35.0姣背 |
瀵害 | 35.0姣背 |
| 鐒￠墰鐙�鎱�(t脿i)/ RoHS鐙�鎱�(t脿i) | 鐒￠墰/绗﹀悎RoHS妯欐簴 |
| 婵曞害鏁忔劅搴︾瓑绱�(MSL) | 4(72灏忔檪) |
XC5VLX155-1FFG1153C绗﹁櫉
XC5VLX155-1FFG1153C鑵冲嵃
