鍨嬭櫉锛歑C5VLX110T-2FFG1738I
銆�銆�绯诲垪锛歏irtex-5
銆�銆�灏佽�濓細FFG1738
銆�銆�閫熷害绛夌礆锛�-2
銆�銆�閭忚集鍠�鍏冩��(sh霉)锛氱磩110K
銆�銆�RAM瀹归噺锛氱磩5.4Mb
銆�銆�DSP Slice鏁�(sh霉)閲忥細960
銆�銆�宸ヤ綔闆诲�擄��1.0V鏍稿績闆诲��
銆�銆�I/O闆诲�擄��1.8V, 2.5V, 3.3V
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Master Parallel绛�
銆�銆�婧�搴﹁寖鍦嶏細鍟嗘��(y猫)绱�(0掳C鑷�70掳C)鎴栧伐妤�(y猫)绱�(-40掳C鑷�100掳C)
銆�銆�灏佽�濆昂瀵革細绱�40mm x 40mm

XC5VLX110T-2FFG1738I鍏锋湁浠ヤ笅涓昏�佺壒鎬э細
銆�銆�1. 楂樻�ц兘鏋舵��(g貌u)锛氬熀浜嶢SMBL锛圓dvanced Silicon Modular Block Layer锛夋灦妲�(g貌u)瑷�(sh猫)瑷�锛屾彁渚涢珮鏁堢殑閭忚集鍜岃矾鐢辫硣婧�銆�
銆�銆�2. 鍏�(n猫i)缃�瀛樺劜鍣�锛氬寘鍚獴lock RAM鍜屽垎甯冨紡RAM锛岃兘澶�?q奴)宕縁(xi脿n)寰�(f霉)闆滅殑瀛樺劜鍣ㄧ�＄悊鍜屾��(sh霉)鎿�(j霉)绶╂矕銆�
銆�銆�3. DSP Slice锛氭瘡鍊婦SP Slice鍖呭惈涔樻硶鍣�銆佺疮鍔犲櫒鍙婂瘎瀛樺櫒锛岄仼鍚堥��(j矛n)琛屾暩(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�(w霉)銆�
銆�銆�4. 楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛氭敮鎸侀珮閬�(d谩)6.5Gbps鐨勪覆琛岄�ｆ帴閫熺巼锛岄仼鐢ㄤ簬PCI Express銆乆AUI绛夊�氱ó鍗�(xi茅)璀�銆�
銆�銆�5. 澶氱ó閰嶇疆閬搁爡锛氭敮鎸佸緸澶栭儴闁冨瓨鍟熷嫊锛屼篃鍙�浠ラ�氶亷JTAG鎴栦富/寰炰覆琛屾帴鍙ｉ��(j矛n)琛屽嫊鎱�(t脿i)閲嶆柊閰嶇疆銆�
銆�銆�6. 鍙�鎿村睍鎬э細鏀�鎸佸�氳姱鐗囨嫾鎺ュ拰閮ㄥ垎閲嶉厤缃�鍔熻��锛屼究浜庢��(g貌u)寤烘洿澶ц��(gu墨)妯＄殑绯荤当(t菕ng)銆�
銆�銆�7. 鍔熻�楀劒(y艒u)鍖栵細閲囩敤Power-on-a-Chip鎶�琛�(sh霉)锛屽叿鍌欎綆鍔熻�楀緟姗熸ā寮忎互鍙婂嫊鎱�(t脿i)闆绘簮绠＄悊鍔熻兘銆�

XC5VLX110T-2FFG1738I閬╃敤浜庝互涓嬮牁(l菒ng)鍩燂細
銆�銆�1. 閫氫俊瑷�(sh猫)鍌欙細濡傜劇绶氬熀绔欍�佽矾鐢卞櫒鍜屼氦鎻涙�熶腑鐢ㄤ綔淇¤櫉铏曠悊鏍稿��銆�
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細鐢ㄤ簬瀵︽檪瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓�炲挤浠ュ強鍏朵粬澶氬獟楂旀��(y墨ng)鐢ㄣ��
銆�銆�3. 宸ユキ(y猫)鑷�鍕曞寲锛氬�︾従(xi脿n)寰�(f霉)闆滄帶鍒剁畻娉曞拰楂橀�熸暩(sh霉)鎿�(j霉)閲囬泦銆�
銆�銆�4. 閱�(y墨)鐧傚剙鍣�锛氭敮鎸侀��(y墨)瀛�(xu茅)褰卞儚铏曠悊銆佹偅鑰呯洠(ji膩n)璀风瓑鍔熻兘銆�
銆�銆�5. 鑸�绌鸿埅澶╋細婊胯冻鑻涘埢鐠�(hu谩n)澧冧笅鐨勮▓绠楅渶姹傦紝渚嬪�傝��(w猫i)鏄熼�氫俊鍜岄浄閬�(d谩)绯荤当(t菕ng)銆�
銆�銆�6. 鏁�(sh霉)鎿�(j霉)涓�蹇冿細鐐烘湇鍕�(w霉)鍣ㄥ姞閫熷崱鎻愪緵闈堟椿鐨勭‖浠跺姞閫熻兘鍔�銆�
銆�銆�7. 娓�瑭︽脯閲忥細浣滅偤楂樻�ц兘娓�瑭﹀剙鍣ㄧ殑鏍稿績铏曠悊鍣ㄤ欢銆�

XC5VLX110T-1FFG1738I
銆�銆�XC5VLX110T-3FFG1738I