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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XC5VLX110-2FFG1760C

XC5VLX110-2FFG1760C 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2025/4/29 16:30:14 鏌ョ湅 闁辫畝锛�33

XC5VLX110-2FFG1760C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪 FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛変腑鐨勪竴鍝�銆傝┎绯诲垪 FPGA 闈㈠悜楂樻�ц兘瑷�(j矛)绠楀拰寰�(f霉)闆滈倧杓ō(sh猫)瑷�(j矛)锛屾敮鎸佸绋�氫俊鍗�(xi茅)璀板拰鎺ュ彛妯�(bi膩o)婧�(zh菙n)銆俈irtex-5 鍩轰簬 65nm 宸ヨ棟鎶�琛�(sh霉)鍒堕��锛屽叿鏈夎睈瀵岀殑閭忚集璩囨簮銆佹暩(sh霉)瀛椾俊铏熻檿鐞� (DSP) 妯″浠ュ強楂橀�熶覆琛屾敹鐧�(f膩)鍣ㄣ��
銆�銆�Virtex-5 LX110 灞簬 LX 瀹舵棌锛屼富瑕侀嚌灏嶉倧杓瘑闆嗗瀷鎳�(y墨ng)鐢�锛屽叾鍏�(n猫i)閮ㄨ硣婧愬寘鎷ぇ閲忕殑 CLB锛堥厤缃倧杓锛夈�丅lock RAM 鍜� DSP Slice銆傞�欐鍣ㄤ欢閬╃敤浜庨渶瑕侀珮閭忚集瀵嗗害鍜岄珮鎬ц兘鐨勫牬鍚堬紝濡傜恫(w菐ng)绲�(lu貌)浜ゆ彌姗�(j墨)銆佽矾鐢卞櫒銆佸湒鍍忚檿鐞嗗拰娓│娓噺瑷�(sh猫)鍌�銆�

鍙冩暩(sh霉)

鍨嬭櫉锛歑C5VLX110-2FFG1760C
銆�銆�绯诲垪锛歏irtex-5
銆�銆�瀹舵棌锛歀X
銆�銆�灏佽锛欶F绛夌礆锛�-2
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 110K
銆�銆�Block RAM 绺介噺锛氱磩 4.9 Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細360
銆�銆�閰嶇疆妯″紡锛歋electMAP, Master/Slave SPI, Boundary Scan
銆�銆�I/O 寮曡叧鏁�(sh霉)锛氭渶澶� 848
銆�銆�宸ヤ綔闆诲锛�1.0V 鏍稿績闆诲 / 1.8V 鎴� 2.5V I/O 闆诲
銆�銆�宸ヨ棟绡�(ji茅)榛�(di菐n)锛�65nm

鐗规��

XC5VLX110-2FFG1760C 鎻愪緵浜嗗挤(qi谩ng)澶х殑鍔熻兘鍜岄潏娲绘��锛屾豢瓒冲悇绋京(f霉)闆滅郴绲�(t菕ng)闇�姹傘��
銆�銆�1. 楂樻�ц兘鏋舵(g貌u)锛歏irtex-5 LX110 閲囩敤鍎�(y艒u)鍖栫殑 6 杓稿叆鏌ユ壘琛� (LUT)锛屾彁鍗囦簡閭忚集鍒╃敤鐜囧拰鏅傚簭鎬ц兘銆�
銆�銆�2. 鍏�(n猫i)缃� DSP 妯″锛氬寘鍚� 360 鍊嬪皥鐢� DSP Slice锛屾瘡鍊� Slice 鏀寔楂橀仈(d谩) 24x18 浣嶄箻娉曠疮鍔犻亱(y霉n)绠�锛岄仼鍚堥煶闋汇�佽闋诲強閫氫俊淇¤櫉铏曠悊銆�
銆�銆�3. 澶у閲� Block RAM锛氭彁渚涘閬�(d谩) 4.9Mb 鐨勫垎甯冨紡瀛樺劜鍣ㄥ拰濉婂瓨鍎插櫒锛岀敤浜庢暩(sh霉)鎿�(j霉)绶╂矕鍜� FIFO 瀵�(sh铆)鐝�(xi脿n)銆�
銆�銆�4. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細鐩＄ LX 瀹舵棌鏈泦鎴愰珮閫熸敹鐧�(f膩)鍣�锛屼絾閫氶亷澶栨帴 PHY 鑺墖鍙摯(ku貌)灞曡嚦鍗冨厗浠ュお缍�(w菐ng)鎴� PCIe 鎺ュ彛銆�
銆�銆�5. 鍙潬鎬у寮�(qi谩ng)锛氭敮鎸佸収(n猫i)寤鸿嚜妾� (BIST) 鍔熻兘鍜� ECC 閷鏍℃姗�(j墨)鍒�锛屾彁楂樼郴绲�(t菕ng)閬�(y霉n)琛岀┅(w臎n)瀹氭�с��
銆�銆�6. 浣庡姛鑰楄ō(sh猫)瑷�(j矛)锛氬埄鐢ㄥ厛閫�(j矛n)鐨勯浕婧愮鐞嗘妧琛�(sh霉)锛屽湪淇濊瓑鎬ц兘鐨勫悓鏅傛笡灏戣兘婧愭秷鑰�銆�
銆�銆�7. 鏄撶敤鎬ч枊鐧�(f膩)宸ュ叿锛氶厤鍚� Xilinx ISE Design Suite锛岀啊鍖栧緸瑷�(sh猫)瑷�(j矛)杓稿叆鍒伴(y脿n)璀夌殑鏁村�嬫祦绋�銆�

鎳�(y墨ng)鐢�

XC5VLX110-2FFG1760C 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬澶氬�嬮牁(l菒ng)鍩燂細
銆�銆�1. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂斤細鍖呮嫭鍩虹珯鎺у埗鍣�銆佺劇绶氭帴鍏ラ粸(di菐n)鍜屽厜鍌宠几骞宠嚭銆�
銆�銆�2. 鏁�(sh霉)鎿�(j霉)涓績鑸囨湇鍕�(w霉)鍣細瀵�(sh铆)鐝�(xi脿n)楂樻晥鐨勬暩(sh霉)鎿�(j霉)鍖呭垎椤�銆佽綁(zhu菐n)鐧�(f膩)鍜岃矤(f霉)杓夊潎琛�銆�
銆�銆�3. 瑕栭牷寤ｆ挱瑷�(sh猫)鍌欙細鏀寔瀵�(sh铆)鏅傜法纰艰В纰�銆佸湒褰㈢枈鍔犲拰澶氶�氶亾鍒囨彌銆�
銆�銆�4. 閱�(y墨)鐧傚奖鍍忕郴绲�(t菕ng)锛氬姞閫熻秴鑱叉尝銆丆T 鍜� MRI 鐨勫湒鍍忛噸寤洪亷绋�銆�
銆�銆�5. 宸ユキ(y猫)鑷嫊鍖栵細璨�(f霉)璨�(z茅)閬�(y霉n)鍕曟帶鍒躲�佹(j墨)鍣ㄤ汉瑕栬鍜岄爯(y霉)娓�х董璀�(h霉)绠楁硶鍩�(zh铆)琛�銆�
銆�銆�6. 娓│娓噺鍎�鍣細濡傜ず娉㈠櫒銆侀牷璀滃垎鏋愬剙绛夊皪閲囨ǎ鐜囧拰绮惧害鏈夋サ楂樿姹傜殑鐢�(ch菐n)鍝�銆�
銆�銆�7. 杌嶄簨鑸ぉ闋�(l菒ng)鍩燂細绗﹀悎鍤�(y谩n)鑻涚挵(hu谩n)澧冩浠朵笅鐨勪换鍕�(w霉)闂�(gu膩n)閸靛瀷鎳�(y墨ng)鐢�銆�

鏇夸唬鍨嬭櫉

XC5VLX110T-2FFG1760C

xc5vlx110-2ffg1760c鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xc5vlx110-2ffg1760c鐢�(ch菐n)鍝�

xc5vlx110-2ffg1760c鍙冩暩(sh霉)

  • 妯�(bi膩o)婧�(zh菙n)鍖呰1
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛�
  • 绯诲垪Virtex®-5 LX
  • LAB/CLB鏁�(sh霉)8640
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)110592
  • RAM 浣嶇附瑷�(j矛)4718592
  • 杓稿叆/杓稿嚭鏁�(sh霉)800
  • 闁�鏁�(sh霉)-
  • 闆绘簮闆诲0.95 V ~ 1.05 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害0°C ~ 85°C
  • 灏佽/澶栨1760-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�1760-FCBGA
  • 閰嶇敤568-5088-ND - BOARD DEMO DAC1408D750HW-V5-ML523-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1760-500-G-ND - BOARD DEV VIRTEX 5 FF1760