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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XC5VLX110-2FF1760C

XC5VLX110-2FF1760C 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2025/4/27 13:22:33 鏌ョ湅 闁辫畝锛�30

XC5VLX110-2FF1760C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪 FPGA 鑺墖涓殑涓�鍝�銆俈irtex-5 绯诲垪閲囩敤鍏堥��(j矛n)鐨� 65nm 宸ヨ棟鍒堕��锛屾彁渚涢珮鎬ц兘銆侀珮瀵嗗害鍜屼綆鍔熻�楃殑瑙ｆ焙鏂规銆俋C5VLX110-2FF1760C 鐗瑰垾閬╃敤浜庨渶瑕佸京(f霉)闆滈倧杓檿鐞�銆侀珮閫熸暩(sh霉)鎿�(j霉)鍌宠几浠ュ強澶ц(gu墨)妯℃暩(sh霉)瀛椾俊铏熻檿鐞嗙殑鎳�(y墨ng)鐢ㄥ牬鏅�銆�
銆�銆�瑭插瀷铏熶腑鐨� XC 琛ㄧず Xilinx 鍏徃鐨� FPGA 绯诲垪锛�5 琛ㄧず绗簲浠� Virtex 绯诲垪锛孷LX110 琛ㄧず鍏烽珨鐨� FPGA 鍣ㄤ欢瀹归噺绛夌礆锛�-2 琛ㄧず閫熷害绛夌礆锛孎(xi脿n)F1760 琛ㄧず灏佽椤炲瀷鍙婂紩鑵虫暩(sh霉)锛孋 琛ㄧず鍟嗙敤婧害鑼冨湇銆�

鍙冩暩(sh霉)

閭忚集鍠厓鏁�(sh霉)閲忥細114,400
銆�銆�閰嶇疆瀛樺劜鍣ㄤ綅鏁�(sh霉)锛�18,369,920
銆�銆�DSP Slice 鏁�(sh霉)閲忥細480
銆�銆�Block RAM 瀹归噺锛�5,184 Kb
銆�銆�I/O 鏁�(sh霉)閲忥細844
銆�銆�鏈�澶у伐浣滈牷鐜囷細550 MHz
銆�銆�宸ヨ棟绡�(ji茅)榛�(di菐n)锛�65 nm
銆�銆�渚涢浕闆诲锛�1.0V 鏍稿績闆诲锛�1.8V I/O 闆诲
銆�銆�灏佽椤炲瀷锛欶FG1760锛�1760 寮曡叧锛�
銆�銆�婧害鑼冨湇锛�0掳C 鑷� 85掳C锛堝晢鐢ㄧ礆锛�

鐗规��

XC5VLX110-2FF1760C 鎻愪緵浜嗚睈瀵岀殑鐗规��锛屽寘鎷絾涓嶉檺浜庝互涓嬪咕榛�(di菐n)锛�
銆�銆�1. 楂樻�ц兘鏋舵(g貌u)锛氬熀浜� Virtex-5 骞宠嚭锛屾敮鎸佸京(f霉)闆滅殑閭忚集閬�(y霉n)绠楀拰骞惰铏曠悊銆�
銆�銆�2. 鍏�(n猫i)缃� DSP 妯″锛氬叿鏈� 480 鍊� DSP Slice锛岄仼鐢ㄤ簬楂橀�熸暩(sh霉)瀛椾俊铏熻檿鐞嗘噳(y墨ng)鐢ㄣ��
銆�銆�3. 澶у閲� Block RAM锛氬叿鍌� 5,184 Kb 鐨� Block RAM锛屽彲瀵�(sh铆)鐝�(xi脿n)娣卞害鏁�(sh霉)鎿�(j霉)绶╂矕鍜屽瓨鍎插姛鑳姐��
銆�銆�4. 鏀寔澶氱ó鎺ュ彛妯�(bi膩o)婧�(zh菙n)锛氬寘鎷� PCI Express銆佸崈鍏嗕互澶恫(w菐ng) MAC 鍜� RocketIO 绛�锛屾豢瓒充笉鍚岄�氫俊闇�姹傘��
銆�銆�5. 鍕曟厠(t脿i)鍙噸閰嶇疆鎶�琛�(sh霉)锛氭敮鎸侀儴鍒嗗崁(q奴)鍩熷嫊鎱�(t脿i)閲嶉厤缃�锛屾彁鍗囩郴绲�(t菕ng)闈堟椿鎬у拰鏁堢巼銆�
銆�銆�6. 浣庡姛鑰楄ō(sh猫)瑷堬細閫氶亷 PowerPC 鍜� Clock Management 鎶�琛�(sh霉)鍎�(y艒u)鍖栧姛鑰楄〃鐝�(xi脿n)銆�
銆�銆�閫欎簺鐗规�т娇寰� XC5VLX110-2FF1760C 鎴愮偤楂樼宓屽叆寮忕郴绲�(t菕ng)銆侀�氫俊瑷�(sh猫)鍌欏拰鍦栧儚铏曠悊闋�(l菒ng)鍩熺殑鐞嗘兂閬告搰銆�

鎳�(y墨ng)鐢�

瑭茶姱鐗囧唬娉涙噳(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂斤細濡傝矾鐢卞櫒銆佷氦鎻涙(j墨)銆佸熀绔欑瓑瑷�(sh猫)鍌欎腑鐨勬牳蹇冧俊铏熻檿鐞嗘ā濉�銆�
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銆�銆�5. 闃插嫏(w霉)鑸囪埅绌鸿埅澶╋細閬╃敤浜庨浄閬�(d谩)绯荤当(t菕ng)銆佽(w猫i)鏄熼�氫俊鍜屽叾浠栭珮鍙潬鎬ф噳(y墨ng)鐢ㄥ牬鏅�銆�
銆�銆�6. 楂樻�ц兘瑷堢畻锛氱敤浣滃崝(xi茅)铏曠悊鍣ㄦ垨鍔犻�熷櫒锛屽煼(zh铆)琛屽ぇ瑕�(gu墨)妯″苟琛岃▓绠椾换鍕�(w霉)銆�
銆�銆�鍏堕珮搴﹂泦鎴愬寲鐨勮ō(sh猫)瑷堝拰寮�(qi谩ng)澶х殑铏曠悊鑳藉姏浣垮叾鑳藉鎳�(y墨ng)灏嶅悇绋京(f霉)闆滅殑宸ヤ綔璨�(f霉)杓�銆�

鏇夸唬鍨嬭櫉

XC5VLX110T-2FF1760C
銆�銆�XC5VLX110T-2FF1136C
銆�銆�XC5VLX110-2FF1136C

xc5vlx110-2ff1760c鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xc5vlx110-2ff1760c鍙冩暩(sh霉)

  • 妯�(bi膩o)婧�(zh菙n)鍖呰1
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛�
  • 绯诲垪Virtex®-5 LX
  • LAB/CLB鏁�(sh霉)8640
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)110592
  • RAM 浣嶇附瑷�4718592
  • 杓稿叆/杓稿嚭鏁�(sh霉)800
  • 闁�鏁�(sh霉)-
  • 闆绘簮闆诲0.95 V ~ 1.05 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害0°C ~ 85°C
  • 灏佽/澶栨1760-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�1760-FCBGA
  • 閰嶇敤568-5088-ND - BOARD DEMO DAC1408D750HW-V5-ML523-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1760-500-G-ND - BOARD DEV VIRTEX 5 FF1760