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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺(c猫)

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XC5VLX110-1FFG1760I

XC5VLX110-1FFG1760I 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2025/5/7 9:55:10 鏌ョ湅 闁辫畝锛�20

XC5VLX110-1FFG1760I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪 FPGA 鑺墖涓殑涓�鍝�銆俈irtex-5 绯诲垪閲囩敤 65nm 宸ヨ棟鍒堕��锛屽叿鏈夐珮鎬ц兘銆侀珮閭忚集瀵嗗害鍜岃睈瀵岀殑宓屽叆寮忓姛鑳芥ā濉婏紝閬╃敤浜庨�氫俊銆佽粛浜�銆佽埅绌鸿埅澶┿�侀啱(y墨)鐧傛垚鍍�銆佸唬鎾互鍙婂伐妤�(y猫)鑷嫊(d貌ng)鍖栫瓑澶氬��(g猫)闋�(l菒ng)鍩�銆�
銆�銆�Virtex-5 绯诲垪 FPGA 鎻愪緵浜嗗绋笉鍚岀殑鏋舵(g貌u)閬告搰锛屽寘鎷� LX锛圠ogic锛夌郴鍒�锛屼富瑕侀嚌灏�(du矛)閫氱敤閭忚集瑷�(sh猫)瑷�(j矛)銆俋C5VLX110 灞簬 LX 绯诲垪锛屾搧鏈� 110K 閭忚集鍠厓锛屾敮鎸� DDR2/DDR3 鎺у埗鍣�銆丳CI Express銆佸崈鍏嗕互澶恫(w菐ng)绛夌‖鏍告ā濉�锛屽悓鏅�(sh铆)鍏峰倷寮�(qi谩ng)澶х殑 DSP 鍔熻兘銆�

鍙冩暩(sh霉)

鍨嬭櫉(h脿o)锛歑C5VLX110-1FFG1760I
銆�銆�绯诲垪锛歏irtex-5 LX
銆�銆�宸ヨ棟锛�65nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細110,000
銆�銆�閰嶇疆瀛樺劜(ch菙)椤炲瀷锛歋RAM
銆�銆�杓稿叆/杓稿嚭寮曡叧鏁�(sh霉)锛�840
銆�銆�鏈�澶х敤鎴� I/O锛�596
銆�銆�鍏�(n猫i)閮ㄥ瓨鍎�(ch菙)鍣細2.5 Mb (鍒嗗竷寮� RAM 鍜屽鐙� RAM)
銆�銆�DSP Slice 鏁�(sh霉)閲忥細220
銆�銆�鏅�(sh铆)閻樿硣婧愶細鏁�(sh霉)瀛楁檪(sh铆)閻樼鐞嗘ā濉� (DCM)锛孭LL
銆�銆�灏佽锛欶FG1760
銆�銆�閫熷害绛夌礆(j铆)锛�-1
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱�(j铆)锛�0掳C 鑷� 85掳C锛�
銆�銆�闆绘簮闆诲锛氬収(n猫i)鏍搁浕澹� 1.0V锛岃紨鍔╅浕澹� 1.5V锛孖/O 闆诲 1.8V/2.5V/3.3V

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XC5VLX110-1FFG1760I 鐨勯棞(gu膩n)閸电壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘閭忚集绲�(ji茅)妲�(g貌u)锛氭敮鎸侀珮閬�(d谩) 533 MHz 鐨勭郴绲�(t菕ng)闋荤巼锛堣鍏烽珨瑷�(sh猫)瑷�(j矛)鑰屽畾锛�銆�
銆�銆�2. 宓屽叆寮忕‖鏍� IP 妯″锛氬寘鍚� PCI Express Endpoint Block銆丷ocketIO 鏀剁櫦(f膩)鍣紙閫熺巼楂橀仈(d谩) 6.5 Gbps锛�锛屼互鍙婂崈鍏嗕互澶恫(w菐ng) MAC 绛�銆�
銆�銆�3. 寮�(qi谩ng)澶х殑 DSP 鏀寔锛氭瘡鍊�(g猫) DSP Slice 鍖呭惈灏堢敤鐨勪箻娉曞櫒鍜岀疮鍔犲櫒锛岄仼鍚堥珮閫熶俊铏�(h脿o)铏曠悊鎳�(y墨ng)鐢ㄣ��
銆�銆�4. 鍏�(n猫i)閮ㄥ瓨鍎�(ch菙)鍣細闆嗘垚澶ч噺鐨� BRAM 鍜屽垎甯冨紡 RAM锛屽彲鐢ㄤ簬 FIFO 绶╂矕鍗�(q奴)銆佹煡鎵捐〃鍜屽叾浠栨暩(sh霉)鎿�(j霉)瀛樺劜(ch菙)闇�姹�銆�
銆�銆�5. 鍙摯(ku貌)灞曟�э細鏀寔澶氱ó澶栭儴鎺ュ彛妯�(bi膩o)婧�(zh菙n)锛屼緥濡� DDR2/DDR3 鍏�(n猫i)瀛樻帶鍒跺櫒銆丩VDS 鎺ュ彛绛�銆�
銆�銆�6. 閰嶇疆鏂瑰紡闈堟椿锛氭敮鎸佸緸涓茶 PROM銆侀杻瀛樻垨涓昏檿鐞嗗櫒鍔犺級閰嶇疆鏁�(sh霉)鎿�(j霉)锛岄倓鏀寔 JTAG 鎺ュ彛閫�(j矛n)琛岃(di脿o)瑭�銆�
銆�銆�7. 浣庡姛鑰楀劒(y艒u)鍖栵細閫氶亷鍕�(d貌ng)鎱�(t脿i)鍔熻�楃鐞嗘妧琛�(sh霉)锛岄檷浣庨亱(y霉n)琛屼腑鐨勮兘婧愭秷鑰�銆�

鎳�(y墨ng)鐢�

瑭茶姱鐗囧唬娉涙噳(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 鏁�(sh霉)鎿�(j霉)閫氫俊瑷�(sh猫)鍌欙細濡傝矾鐢卞櫒銆佷氦鎻涙(j墨)鍜岀恫(w菐ng)绲�(lu貌)鍔犻�熷崱銆�
銆�銆�2. 宸ユキ(y猫)鎺у埗锛氬(sh铆)鏅�(sh铆)铏曠悊鑸囧京(f霉)闆滄帶鍒剁畻娉曞(sh铆)鐝�(xi脿n)銆�
銆�銆�3. 鍦栧儚铏曠悊锛氱敤浜庤闋荤法纰艰В纰�銆佸湒鍍忓寮�(qi谩ng)鍜屾ā寮忚瓨(sh铆)鍒�銆�
銆�銆�4. 閱�(y墨)鐧傝ō(sh猫)鍌欙細瓒呰伈娉㈡垚鍍忋�丆T 鎺冩弿绛夐珮绮惧害瑷�(j矛)绠椾换鍕�(w霉)銆�
銆�銆�5. 杌嶄簨鍙婅埅澶╋細闆烽仈(d谩)淇¤櫉(h脿o)铏曠悊銆佽(w猫i)鏄熼�氫俊銆佸皫(d菐o)鑸郴绲�(t菕ng)闁嬬櫦(f膩)銆�
銆�銆�6. 娓│娓噺鍎�鍣細楂橀�熸暩(sh霉)鎿�(j霉)閲囬泦鑸囧垎鏋愯ō(sh猫)鍌�銆�
銆�銆�鐢变簬鍏跺挤(qi谩ng)澶х殑鍙法绋嬭兘鍔涘拰璞愬瘜鐨勮硣婧�锛孹C5VLX110-1FFG1760I 鎴愮偤鐪惧寰�(f霉)闆滃祵鍏ュ紡绯荤当(t菕ng)鐨勭悊鎯抽伕鎿�銆�

鏇夸唬鍨嬭櫉(h脿o)

XC5VLX110T-1FFG1760I
銆�銆�XC5VLX110T-1FF1760I
銆�銆�XC5VLX110-1FF1136I

xc5vlx110-1ffg1760i鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�(h脿o)
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉(h脿o)
  • 瑭㈠児(ji脿)

xc5vlx110-1ffg1760i鐢�(ch菐n)鍝�

xc5vlx110-1ffg1760i鍙冩暩(sh霉)

  • 妯�(bi膩o)婧�(zh菙n)鍖呰1
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛�
  • 绯诲垪Virtex®-5 LX
  • LAB/CLB鏁�(sh霉)8640
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)110592
  • RAM 浣嶇附瑷�(j矛)4718592
  • 杓稿叆/杓稿嚭鏁�(sh霉)800
  • 闁�鏁�(sh霉)-
  • 闆绘簮闆诲0.95 V ~ 1.05 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害-40°C ~ 100°C
  • 灏佽/澶栨1760-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�1760-FCBGA
  • 閰嶇敤568-5088-ND - BOARD DEMO DAC1408D750HW-V5-ML523-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1760-500-G-ND - BOARD DEV VIRTEX 5 FF1760