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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XC5VLX110-1FF1760C

XC5VLX110-1FF1760C 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2025/4/30 15:44:27 鏌ョ湅 闁辫畝锛�33

XC5VLX110-1FF1760C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏�銆俈irtex-5 绯诲垪 FPGA 鍩轰簬鍏堥��(j矛n)鐨� 65nm 宸ヨ棟鎶�琛�(sh霉)鍒堕��锛屽叿鏈夐珮鎬ц兘銆侀珮瀵嗗害鍜屼綆鍔熻�楃殑鐗归粸(di菐n)銆俋C5VLX110-1FF1760C 鎻愪緵璞愬瘜鐨勯倧杓硣婧�銆佸祵鍏ュ紡瀛樺劜鍣ㄦā濉娿�丏SP 妯″浠ュ強楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛岄仼鐢ㄤ簬閫氫俊銆佷俊铏熻檿鐞�銆佸湒鍍忚檿鐞嗙瓑澶氱ó寰�(f霉)闆滄噳(y墨ng)鐢ㄩ牁(l菒ng)鍩熴��
銆�銆�瑭茶姱鐗囬倓鏀寔澶氱ó閰嶇疆閬搁爡(xi脿ng)锛屽寘鎷緸闁冨瓨鍟熷嫊鎴栭�氶亷 JTAG 鎺ュ彛閫�(j矛n)琛岀法绋嬶紝鎻愪緵浜嗛珮搴︾殑闈堟椿鎬у拰鍙潬鎬�銆�

鍙冩暩(sh霉)

绯诲垪锛歏irtex-5
銆�銆�鍨嬭櫉锛歑C5VLX110-1FF1760C
銆�銆�宸ヨ棟锛�65nm
銆�銆�FPGA 鏋舵(g貌u)锛歀UT-based
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 110,000 鍊�
銆�銆�Block RAM锛�3,990 Kb
銆�銆�DSP48 Slice 鏁�(sh霉)閲忥細220
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細鏈�澶� 1,040 鍊�
銆�銆�涓茶鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂� 11.18 Gbps
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� 85掳C锛�
銆�銆�灏佽椤炲瀷锛欶FG1760 (1760-Pin Fine Pitch BGA)

鐗规��

XC5VLX110-1FF1760C 鎻愪緵浜嗗崜瓒婄殑鎬ц兘鍜岄泦鎴愬害锛屾槸 Virtex-5 绯诲垪涓純鐐洪珮绔殑鍨嬭櫉涔嬩竴銆傚叾涓昏鐗规�у寘鎷細
銆�銆�1. 楂樺閲忛倧杓硣婧�锛岃兘澶�?q奴)宕縁(xi脿n)寰�(f霉)闆滅殑鏁�(sh霉)瀛楅浕璺ō(sh猫)瑷�(j矛)銆�
銆�銆�2. 鍏�(n猫i)缃ぇ瀹归噺 Block RAM锛屾敮鎸�?j菒n)?sh霉)鎿�(j霉)绶╂矕鍜屽瓨鍎插姛鑳�銆�
銆�銆�3. DSP48 Slice 鐨勫姞鍏ヤ娇鍏跺湪鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�(w霉)涓〃鐝�(xi脿n)鍎�(y艒u)鐣�锛屼緥濡傛烤娉��丗FT 鍜岀煩闄ｉ亱(y霉n)绠楃瓑銆�
銆�銆�4. 鏀寔楂橀仈(d谩) 11.18 Gbps 鐨勯珮閫熶覆琛屾敹鐧�(f膩)鍣紝閬╁悎闇�瑕侀珮甯跺鏁�(sh霉)鎿�(j霉)鍌宠几?sh霉)鑶�?y墨ng)鐢ㄥ牬鏅�銆�
銆�銆�5. 鎻愪緵闈堟椿鐨� I/O 妯�(bi膩o)婧�(zh菙n)鏀寔锛屽寘鎷� LVCMOS銆丩VDS 绛夊绋父瑕嬫帴鍙ｅ崝(xi茅)璀�銆�
銆�銆�6. 鍏峰倷鍕曟厠(t脿i)鍔熻�楃鐞嗗姛鑳斤紝鍙劒(y艒u)鍖栫郴绲�(t菕ng)鍔熻��銆�
銆�銆�7. 閰嶅悎 Xilinx 鐨勯枊鐧�(f膩)宸ュ叿锛堝 ISE 鎴� Vivado锛�锛屽彲浠ュ揩閫熷畬鎴愯ō(sh猫)瑷�(j矛)杓稿叆銆佺稖鍚�銆佸竷灞�甯冪窔鍙婇(y脿n)璀夈��

鎳�(y墨ng)鐢�

XC5VLX110-1FF1760C 鍥犲叾楂樻�ц兘鍜岄珮闆嗘垚搴�锛屽唬娉涙噳(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 閫氫俊瑷�(sh猫)鍌欙細濡傜劇绶氬熀绔�銆佽矾鐢卞櫒鍜屼氦鎻涙(j墨)涓殑鏁�(sh霉)鎿�(j霉)鍖呰檿鐞嗚垏杞�(zhu菐n)鐧�(f膩)銆�
銆�銆�2. 鍦栧儚鑸囪闋昏檿鐞嗭細瀵�(sh铆)鏅�(sh铆)鍦栧儚澧炲挤(qi谩ng)銆佽闋荤法纰艰В纰肩瓑鍔熻兘銆�
銆�銆�3. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細鐢ㄤ簬鍔犲瘑瑙ｅ瘑銆佸绺В澹撶府绛変换鍕�(w霉)銆�
銆�銆�4. 娓│娓噺鍎�鍣細淇¤櫉鐧�(f膩)鐢熷櫒銆佺ず娉㈠櫒绛夎ō(sh猫)鍌欑殑鏍稿績鎺у埗鍠厓銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忥細瓒呰伈娉㈡垚鍍�銆丆T 鎺冩弿绛夐啱(y墨)鐧傝ō(sh猫)鍌欑殑鏁�(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞嗐��
銆�銆�6. 宸ユキ(y猫)鑷嫊鍖栵細姗�(j墨)鍣ㄤ汉鎺у埗銆侀亱(y霉n)鍕曟帶鍒剁瓑寰�(f霉)闆滃(sh铆)鏅�(sh铆)鎺у埗浠诲嫏(w霉)銆�
銆�銆�7. 鑸┖鑸ぉ鑸囧湅闃诧細闆烽仈(d谩)淇¤櫉铏曠悊銆佽(w猫i)鏄熼�氫俊绛夊皪鍙潬鎬у拰鎬ц兘瑕佹眰妤甸珮鐨勫牬鍚堛��

鏇夸唬鍨嬭櫉

XC5VLX110T-1FF1760C

xc5vlx110-1ff1760c鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児(ji脿)

xc5vlx110-1ff1760c鍙冩暩(sh霉)

  • 妯�(bi膩o)婧�(zh菙n)鍖呰1
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛�
  • 绯诲垪Virtex®-5 LX
  • LAB/CLB鏁�(sh霉)8640
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)110592
  • RAM 浣嶇附瑷�(j矛)4718592
  • 杓稿叆/杓稿嚭鏁�(sh霉)800
  • 闁�鏁�(sh霉)-
  • 闆绘簮闆诲0.95 V ~ 1.05 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害0°C ~ 85°C
  • 灏佽/澶栨1760-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�1760-FCBGA
  • 閰嶇敤568-5088-ND - BOARD DEMO DAC1408D750HW-V5-ML523-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1760-500-G-ND - BOARD DEV VIRTEX 5 FF1760