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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XC5VFX70T-2FFG665I

XC5VFX70T-2FFG665I 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2022/10/21 15:14:32 鏌ョ湅 闁辫畝锛�944

鐢�(ch菐n)鍝佸瀷铏�

XC5VFX70T-2FFG665I

鎻忚堪

IC FPGA 360 I/O 665FCBGA

鍒嗛

闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪)

姒傝堪

鐢�(ch菐n)鍝佸瀷铏�

XC5VFX70T-2FFG665I

鎻忚堪

IC FPGA 360 I/O 665FCBGA

鍒嗛

闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪)

鐢熺敘(ch菐n)寤犲

Xilinx鍏徃

绯诲垪

Virtex?-5 FXT

閮ㄥ垎鐙�鎱�(t脿i)

娲绘��

闆诲-闆绘簮

0.95V~1.05V

宸ヤ綔婧害

-40掳C~100掳C(TJ)

鍖�/绠�

665-BBGA锛孎(xi脿n)CBGA

渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘

665-FCBGA(27x27)

鍩虹(ch菙)閮ㄤ欢铏�

XC5VFX70T

鐗规��

    Virtex-5 FXT锛氬叿鏈夐珮绱氫覆琛岄�ｆ帴鐨勯珮鎬ц兘宓屽叆寮忕郴绲�(t菕ng)

    FXT鍣ㄤ欢閲囩敤鍙(di脿o)闆诲瑾�(di脿o)绡�(ji茅)鍣紝鍦ㄥ悓涓�灏佽涓叿鏈夎冻璺″吋瀹规��

    鏈�鍏堥��(j矛n)锛岄珮鎬ц兘锛屾渶浣冲埄鐢ㄧ巼鐨凢PGA鏋舵(g貌u)

    鐪熸鐨�6杓稿叆鏌ユ壘琛�(LUT)鎶�琛�(sh霉)

    闆�5-LUT閬搁爡

    鏀归��(j矛n)鐨勬笡灏戣烦韬嶈矾鐢�

    64浣嶅垎甯冨紡RAM閬搁爡

    SRL32 / Dual SRL16閬搁爡

    寮�(qi谩ng)澶х殑鏅傞悩绠＄悊纾佽布(CMT)鏅傞悩

    鏁�(sh霉)瀛楁檪閻樼鐞嗗櫒(DCM)闃绘闆跺欢閬茬珐娌�锛岄牷鐜囧悎鎴愬拰鏅傞悩鐩哥Щ

    PLL妯″鐢ㄤ簬杓稿叆鎶栧嫊婵炬尝锛岄浂寤堕伈绶╂矕锛岄牷鐜囧悎鎴愬拰鐩镐綅鍖归厤鏅傞悩鍒嗛牷

    36-Kbit Block RAM / FIFO

    鐪熸鐨勯洐绔彛RAM妯″

    澧炲挤(qi谩ng)鐨勫彲閬稿彲绶ㄧ▼FIFO閭忚集

    鍙法绋� - 鐪熸鐨勯洐绔彛瀵害鍙仈(d谩)x36 - 绨″柈鐨勯洐绔彛瀵害鍙仈(d谩)x72

    鍏�(n猫i)缃彲閬哥殑绯鹃尟闆昏矾

    鍙伕鎿囧皣姣忓�嬪绶ㄧ▼鐐哄叐鍊嬬崹(d煤)绔嬬殑18-Kbit濉�

    楂樻�ц兘骞惰SelectIO鎶�琛�(sh霉)

    1.2鑷�3.3VI / O鎿嶄綔

    浣跨敤ChipSync鎶�琛�(sh霉)閫�(j矛n)琛屾簮鍚屾鎺ュ彛

    鏁�(sh霉)瀛楁帶鍒堕樆鎶�(DCI)鏈夋簮绲傜

    闈堟椿鐨勭窗(x矛)绮掑害I / O閵�琛屾キ(y猫)鍕�(w霉)

    楂橀�熷収(n猫i)瀛樻帴鍙ｆ敮鎸�

    鍏堥��(j矛n)鐨凞SP48E鍒囩墖

    25 x 18锛屼簩閫�(j矛n)鍒惰(b菙)纰硷紝涔樻硶

    鍙伕鐨勫姞娉曞櫒锛屾笡娉曞櫒鍜岀疮鍔犲櫒

    鍙伕鐨勬祦姘寸窔

    鍙伕鐨勬寜浣嶉倧杓姛鑳�

    灏堢敤绱氳伅(li谩n)閫ｆ帴

    闈堟椿鐨勯厤缃伕闋�

    SPI鍜屽苟琛孎LASH鎺ュ彛

    鍏锋湁灏堢敤鍥為��閲嶉厤缃倧杓殑澶氭瘮鐗规祦鏀寔

    鑷嫊绺界窔瀵害妾㈡脯鍔熻兘

    鎵�鏈夎ō(sh猫)鍌欎笂鐨勭郴绲�(t菕ng)鐩�(ji膩n)鎺у姛鑳�

    鐗囦笂/鐗囧鐔辩洠(ji膩n)鎺�

    鐗囦笂/鐗囧闆绘簮鐩�(ji膩n)鎺�

    JTAG瑷晱鎵�鏈夊彈鐩�(ji膩n)鎺х殑鏁�(sh霉)閲�

    鐢ㄤ簬PCI Express瑷�(sh猫)瑷堢殑闆嗘垚绔粸(di菐n)妯″

    涓夋ā10/100/1000 Mb / s浠ュお缍�(w菐ng)MAC

    RocketIO GTX鏀剁櫦(f膩)鍣ㄩ�熷害鐐�150 Mb / s鑷�6.5 Gb / s

    TXT鍜孎XT骞宠嚭

    PowerPC 440寰檿鐞嗗櫒

    鍍呴檺FXT骞宠嚭

    RISC鏋舵(g貌u)

    7闅庢绠￠亾

    鍖呮嫭32 KB鐨勬寚浠ゅ拰鏁�(sh霉)鎿�(j霉)绶╁瓨

    鍎�(y艒u)鍖栫殑铏曠悊鍣ㄦ帴鍙ｇ祼(ji茅)妲�(g貌u)(crossbar)

    65绱嶇背閵匔MOS宸ヨ棟鎶�琛�(sh霉)

    1.0V鏍稿績闆诲

    楂樹俊铏熷畬鏁存�у�掕鑺墖灏佽锛屾彁渚涙(bi膩o)婧�(zh菙n)鎴栫劇閴涘皝瑁濋伕闋�


鍙冩暩(sh霉)

鍙法绋嬮倧杓鍨�

鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪

绗﹀悎REACH妯�(bi膩o)婧�(zh菙n)

鏄�

绗﹀悎姝愮洘RoHS妯�(bi膩o)婧�(zh菙n)

鏄�

鐙�鎱�(t脿i)

娲绘��

鏅傞悩闋荤巼-鏈�澶у��

1265.0 MHz

JESD-30浠ｇ⒓

S-PBGA-B665

JESD-609浠ｇ⒓

E1

绺絉AM浣嶆暩(sh霉)

5455872

CLB鏁�(sh霉)閲�

6080.0

杓稿叆鏁�(sh霉)閲�

360.0

閭忚集鍠厓鐨勬暩(sh霉)閲�

71680.0

杓稿嚭鏁�(sh霉)閲�

360.0

绲傜鏁�(sh霉)閲�

665

绲勭箶

6080 CLBS

宄板�煎洖娴佹韩搴�(鈩�)

250

闆绘簮

1,2.5

璩囨牸鐙�鎱�(t脿i)

涓嶅悎鏍�

鍧愬Э楂樺害-鏈�澶�

2.9姣背

瀛愰鍒�

鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪

闆绘簮闆诲

1.0 V

闆绘簮闆诲-鏈�灏忓��

0.95 V

闆绘簮闆诲-鏈�澶у��

1.05 V

瀹夎椤炲瀷

琛ㄩ潰璨艰

鎶�琛�(sh霉)

CMOS

绲傜瀹屾垚

閷�/閵�/閵�(Sn95.5Ag4.0Cu0.5)

绲傜琛ㄦ牸

鐞�

绲傜闁撹窛

1.0姣背

绲傜浣嶇疆

搴曢儴

鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶у��(s)

涓夊崄

闀峰害

27.0姣背

瀵害

27.0姣背

鍖呰楂旀潗鏂�

濉戞枡/鐠�(hu谩n)姘фü鑴�

鍖呰９浠ｇ⒓

BGA

鍖呯瓑鍍逛唬纰�

BGA665,26X26,40

鍖呰褰㈢媭

寤ｅ牬

鍖呰棰�(f膿ng)鏍�

缍�(w菐ng)鏍奸櫍鍒�

鍒堕�犲晢鍖呰瑾槑

27 X 27 MM锛岀劇閴涳紝F(xi脿n)BGA-665

xc5vfx70t-2ffg665i鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xc5vfx70t-2ffg665i璩囨枡 鏇村>

  • 鍨嬭櫉
  • 鎻忚堪
  • 鍝佺墝
  • 闁辫涓嬭級

xc5vfx70t-2ffg665i鍙冩暩(sh霉)

  • 妯�(bi膩o)婧�(zh菙n)鍖呰1
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛�
  • 绯诲垪Virtex®-5 FXT
  • LAB/CLB鏁�(sh霉)5600
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)71680
  • RAM 浣嶇附瑷�5455872
  • 杓稿叆/杓稿嚭鏁�(sh霉)360
  • 闁�鏁�(sh霉)-
  • 闆绘簮闆诲0.95 V ~ 1.05 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害-40°C ~ 100°C
  • 灏佽/澶栨665-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�665-FCBGA
  • 閰嶇敤568-5088-ND - BOARD DEMO DAC1408D750DK-V5-EMBD-ML507-G-J-ND - DEV KIT V5 W/ISM & EDK JAPANDK-V5-EMBD-ML507-G-ND - DEV KIT V5 W/ISM & EDKHW-V5-ML507-UNI-G-ND - EVAL PLATFORM V5 FXT