鏅傞枔锛�2023/8/7 16:37:46
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鐢�(ch菐n)鍝佸瀷铏� | XC5VFX130T-1FF1738I |
鎻忚堪 | IC FPGA 840 I/O 1738FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢熺敘(ch菐n)寤犲 | Xilinx鍏徃 |
绯诲垪 | Virtex?-5 FXT |
閮ㄥ垎鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 0.95V~1.05V |
宸ヤ綔婧害 | -40掳C~100掳C(TJ) |
鍖�/绠� | 1738-BBGA锛孎(xi脿n)CBGA |
渚涙噳鍟嗚ō鍌欏寘 | 1738-FCBGA(42.5x42.5) |
鍩虹閮ㄤ欢铏� | XC5VFX130T |
XC5VFX130T-1FF1738I
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎REACH妯欐簴 | 鏄� |
鐙�鎱�(t脿i) | 娲绘�� |
鏅傞悩闋荤巼-鏈�澶у�� | 1098.0 MHz |
JESD-30浠ｇ⒓ | S-PBGA-B1738 |
JESD-609浠ｇ⒓ | E0 |
绺絉AM浣嶆暩(sh霉) | 10985472 |
CLB鏁�(sh霉)閲� | 11200.0 |
杓稿叆鏁�(sh霉)閲� | 840.0 |
閭忚集鍠厓鐨勬暩(sh霉)閲� | 131072.0 |
杓稿嚭鏁�(sh霉)閲� | 840.0 |
绲傜鏁�(sh霉)閲� | 1738 |
绲勭箶 | 11200 CLBS |
宄板�煎洖娴佹韩搴�(鈩�) | 225 |
闆绘簮 | 1,2.5 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
鍧愬Э楂樺害-鏈�澶� | 3.5姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲 | 1.0 V |
闆绘簮闆诲-鏈�灏忓�� | 0.95 V |
闆绘簮闆诲-鏈�澶у�� | 1.05 V |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
绲傜瀹屾垚 | 閷�/閴�(Sn63Pb37) |
绲傜琛ㄦ牸 | 鐞� |
绲傜闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶у��(s) | 涓夊崄 |
闀峰害 | 42.5姣背 |
瀵害 | 42.5姣背 |
鍖呰楂旀潗鏂� | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰９浠ｇ⒓ | BGA |
鍖呯瓑鍍逛唬纰� | BGA1738,42X42,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰棰ㄦ牸 | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 42.50 X 42.50 MM锛孎(xi脿n)BGA-1738 |
| 灞�� | 鎻忚堪 |
鐒￠墰鐙�鎱�(t脿i)/ RoHS鐙�鎱�(t脿i) | 鍖呭惈閴�/ RoHS涓嶅悎瑕�(gu墨) |
婵曞害鏁忔劅搴︾瓑绱�(MSL) | 4(72灏忔檪) |
XC5VFX130T-1FF1738I绗﹁櫉
XC5VFX130T-1FF1738I鑵冲嵃
XC5VFX130T-1FF1738I灏佽
鍨嬭櫉 | 鍒堕�犲晢 | 鍝佸悕 | 鎻忚堪 |
XC5VFX130T-1FFG1738C | 璩介潏鎬� | FPGA鑺墖 | 11200CLB 098MHz 31072-Cell CMOS PBGA1738 42.50X42.5MM FBGA |
XC5VFX130T-2FFG1738C | 璩介潏鎬� | FPGA鑺墖 | 65nm鎶�琛�(sh霉) 1V 1738Pin FCBGA |
XC5VFX130T-2FFG1738I | 璩介潏鎬� | FPGA鑺墖 | 1V 1738Pin FCBGA |
