XC4VLX80-11FFG1148I 鏅�(sh铆)闁擄細2023/7/7 17:59:02 闁辫畝锛�659

鎻忚堪

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鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸瀷铏�(h脿o)	XC4VLX80-11FFG1148I
鎻忚堪	闆嗘垚闆昏矾FPGA 768 I / O 1148FCBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)
鍒堕€犲晢	Xilinx鍏徃
绯诲垪	Virtex?-4LX
闆诲-闆绘簮	1.14V?1.26V
宸ヤ綔婧害	-40掳C?100掳C(TJ)
鍖呰/绠�	1148-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	1148-FCPBGA(35x35)
鍩烘湰闆朵欢铏�(h脿o)	XC4VLX80

鐢�(ch菐n)鍝佸湒鐗�

XC4VLX80-11FFG1148I

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍒堕€犲晢鍖呰瑾�(shu艒)鏄�	鐒�(w煤)閴�锛孎(xi脿n)BGA-1148
闆朵欢鐙€鎱�(t脿i)	娲绘€�
鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪
鏈€澶ф檪(sh铆)閻橀牷鐜�	1205.0鍏嗚但
JESD-30浠ｇ⒓	S-PBGA-B1148
JESD-609浠ｇ⒓	1
CLB鏁�(sh霉)閲�	8960.0
杓稿叆鏁�(sh霉)閲�	768.0
閭忚集鍠厓鏁�(sh霉)	80640.0
鍑烘暩(sh霉)閲�	768.0
绔瓙鏁�(sh霉)	1148
绲勭箶	8960 CLBS
鍖呰楂旀潗鏂�	濉戞枡/鐠�(hu谩n)姘фü(sh霉)鑴�
鍖呰９浠ｈ櫉(h脿o)	BGA
瑁濈瓑鏁堜唬纰�	BGA1148,34X34,40
鍖呰褰㈢媭	姝ｆ柟褰�
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
宄板€煎洖娴佹韩搴�(鈩�)	245
搴ч珮	3.4姣背
瀛愰鍒�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	1.2浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆(j铆)	宸ユキ(y猫)
绲傜绮惧姞宸�	閷�/閵€/閵�(Sn95.5Ag4.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅�(sh铆)闁揁宄板€煎洖娴佹韩搴�-鏈€澶�(绉�)	30
闀�(zh菐ng)搴�	35.0姣背
瀵害	35.0姣背

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

RoHS鐙€鎱�(t脿i)	绗﹀悎ROHS3
姘村垎鏁忔劅鎬ф按骞�(MSL)	4(72灏忔檪(sh铆))

寮曡叧鍦�

灏佽

XC4VLX80-11FFG1148I灏佽

鏇夸唬鍨嬭櫉(h脿o)

鍨嬭櫉(h脿o)	鍒堕€犲晢	鍝佸悕	鎻忚堪
XC4VLX80-10FFG1148C	璩介潏鎬�	FPGA鑺墖	80640 Cells 90nm Technology 1.2V 1148Pin FCBGA
XC4VLX80-10FFG1148I	璩介潏鎬�	FPGA鑺墖	80640 Cells 90nm Technology 1.2V 1148Pin FCBGA
XC4VLX80-10FF1148I	璩介潏鎬�	FPGA鑺墖	80640 Cells 90nm Technology 1.2V 1148Pin FCBGA