XC4VLX80-10FFG1148I 鏅�(sh铆)闁擄細2023/7/18 18:00:52 闁辫畝锛�213

鎻忚堪

XC4VLX80-10FFG1148I灏囬珮绱氱妯″(ASMBLTM)鏋舵(g貌u)鑸囧悇绋潏娲诲姛鑳界浉绲�(ji茅)鍚�锛屾サ澶у湴澧炲挤(qi谩ng)浜嗗彲绶ㄧ▼閭忚集瑷�(sh猫)瑷�(j矛)鑳藉姏锛屼娇鍏舵垚鐐篈SIC鎶€琛�(sh霉)鐨勫挤(qi谩ng)澶ф浛浠ｅ搧銆俋C4VLX80-10FFG1148I鍖呮嫭涓夊€�(g猫)骞宠嚭绯诲垪鈥斺€擫X銆丗X鍜孲X鈥旀彁渚涘绋姛鑳介伕鎿囧拰绲勫悎渚嗚В姹烘墍鏈夊京(f霉)闆滅殑鎳�(y墨ng)鐢ㄧ▼搴�銆傚唬娉涚殑Virtex-4FPGAhard-lP鍏�(n猫i)鏍告ā濉婂寘鎷琍owerPCR铏曠悊鍣紙甯舵湁鏂扮殑APU鎺ュ彛锛�銆佷笁妯′互澶恫(w菐ng)MAC銆�622Mbls鑷�6.5Gbs涓茶鏀剁櫦(f膩)鍣ㄣ€佸皥鐢―SP鐗�銆侀珮閫熸檪(sh铆)閻樼鐞嗛浕璺拰婧�-鍚屾鎺ュ彛濉�?锛涱姠闀滆叄irtex-4FPGA妲�(g貌u)寤哄鏄皪娴佽鐨刅irtex銆乂irtex-E銆乂irtex-ll銆乂irtex-lPro鍜孷irtex-llProX鐢�(ch菐n)鍝佺郴鍒椾腑鐨勯偅浜涚殑澧炲挤(qi谩ng)锛屽洜姝や笂涓€浠ｈō(sh猫)瑷�(j矛)鍚戜笂鍏煎銆傝┎鍣ㄤ欢閲囩敤鏈€鍏堥€�(j矛n)鐨�90绱嶇背閵呭伐钘濈敓鐢�(ch菐n)锛岄噰鐢�300姣背锛�12鑻卞锛夋櫠鍦撴妧琛�(sh霉)銆�

鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸瀷铏�	XC4VLX80-10FFG1148I
鎻忚堪	闆嗘垚闆昏矾FPGA 768 I / O 1148FCBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鍒堕€犲晢	Xilinx鍏徃
绯诲垪	Virtex?-4LX
鎵撳寘	鎵樼洡
闆诲-闆绘簮	1.14V?1.26V
宸ヤ綔婧害	-40掳C?100掳C(TJ)
鍖呰/绠�	1148-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	1148-FCPBGA(35x35)
鍩烘湰闆朵欢铏�	XC4VLX80

鐢�(ch菐n)鍝佸湒鐗�

XC4VLX80-10FFG1148I

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍒堕€犲晢鍖呰瑾槑	鐒￠墰锛孎(xi脿n)BGA-1148
绗﹀悎姝愮洘RoHS	鏄�
鐙€鎱�(t脿i)	娲绘€�
鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
鏈€澶ф檪(sh铆)閻橀牷鐜�	1028.0鍏嗚但
JESD-30浠ｇ⒓	S-PBGA-B1148
JESD-609浠ｇ⒓	e1
绺絉AM浣�	3686400
CLB鏁�(sh霉)閲�	8960.0
杓稿叆鏁�(sh霉)閲�	768.0
閭忚集鍠厓鏁�(sh霉)	80640.0
杓稿嚭鏁�(sh霉)閲�	768.0
绔瓙鏁�(sh霉)	1148
绲勭箶	8960 CLBS
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA1148,34X34,40
鍖呰褰㈢媭	鍥涙柟褰�
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
宄板€煎洖娴佹韩搴�(鈩�)	245
搴ч珮	3.4姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	1.2浼�
鏈€灏忎緵闆婚浕澹�	1.14浼�
鏈€澶ч浕婧愰浕澹�	1.26浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
绲傜瀹屾垚	閷�/閵€/閵�(Sn95.5Ag4.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅�(sh铆)闁揁宄板€煎洖娴佹韩搴�-鏈€澶у€�(绉�)	30
闀峰害	35.0姣背
瀵害	35.0姣背

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

灞€�	鎻忚堪
RoHS鐙€鎱�(t脿i)	绗﹀悎ROHS3
姘村垎鏁忔劅鎬ф按骞�(MSL)	4(72灏忔檪(sh铆))

寮曡叧鍦�

CAD妯″瀷

XC4VLX80-10FFG1148I绗﹁櫉

XC4VLX80-10FFG1148I鑵冲嵃

灏佽

XC4VLX80-10FFG1148I灏佽

鏇夸唬鍨嬭櫉

鍨嬭櫉	鍒堕€犲晢	鍝佸悕	鎻忚堪
XC4VLX80-10FFG1148C	璩介潏鎬�	FPGA鑺墖	80640鍠厓 90nm鎶€琛�(sh霉) 1.2V 1148Pin FCBGA
XC4VLX80-11FF1148I	璩介潏鎬�	FPGA鑺墖	80640鍠厓 90nm鎶€琛�(sh霉) 1.2V 1148Pin FCBGA