鏅傞枔锛�2025/4/30 16:46:44
闁辫畝锛�33
XC4VLX60-11FFG1148I鏄疿ilinx鍏徃鎺ㄥ嚭鐨刅irtex-4绯诲垪FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛変腑鐨勪竴鍝°�傝┎绯诲垪鑺墖鍩轰簬90nm宸ヨ棟鍒堕��锛岄仼鐢ㄤ簬楂樻�ц兘銆侀珮瀵嗗害鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗗拰閭忚集瑷�(sh猫)瑷堟噳鐢�銆�
銆�銆�XC4VLX60灞簬Virtex-4 LX瀛愮郴鍒�锛屼富瑕侀嚌灏嶉倧杓�ц兘閫茶浜嗗劒(y艒u)鍖�锛屽悓鏅傞泦鎴愪簡璞愬瘜鐨勮硣婧愶紝濡侱SP Slice銆丅lock RAM绛�銆傚畠鍏锋湁寮峰ぇ鐨勯潏娲绘�у拰鍙摯灞曟�э紝閬╁悎鎳夌敤浜庨�氫俊鍩虹(ch菙)瑷�(sh猫)鏂�銆佸湒鍍忚檿鐞�銆佽粛浜嬭埅绌恒�佸伐妤�(y猫)鎺у埗绛夐牁(l菒ng)鍩熴��
鍨嬭櫉锛歑C4VLX60-11FFG1148I
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歏irtex-4 LX
銆�銆�灏佽椤炲瀷锛欶FG1148
銆�銆�I/O寮曡叧鏁�(sh霉)锛�572
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Master Parallel
銆�銆�閰嶇疆瀛樺劜鍣細澶栭儴閰嶇疆瀛樺劜鍣ㄦ敮鎸�
銆�銆�FPGA鏋舵(g貌u)锛歋RAM-based
銆�銆�閭忚集鍠厓鏁�(sh霉)锛氱磩60,000鍊婼lices
銆�銆�姣忓�婼lice鍖呭惈锛�4鍊�6杓稿叆LUT
銆�銆�Block RAM澶�?銆傛澀s3.5Mb
銆�銆�DSP Slices鏁�(sh霉)閲忥細204
銆�銆�鏈�澶у伐浣滈牷鐜囷細瓒呴亷400MHz锛堣鍏烽珨瑷�(sh猫)瑷堣�屽畾锛�
銆�銆�闆绘簮闆诲锛�1.2V Core Voltage锛�3.3V Auxiliary Voltage
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C鑷�70掳C锛夛紝宸ユキ(y猫)绱氾紙-40掳C鑷�100掳C锛�
XC4VLX60 FPGA鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘閭忚集绲�(ji茅)妲�(g貌u)锛氶噰鐢ㄤ簡鏀归�插瀷Slice鏋舵(g貌u)锛屾彁渚涗簡鏇撮珮鐨勯倧杓瘑搴﹀拰鎬ц兘銆�
銆�銆�2. 鍏�(n猫i)宓孌SP Slice锛氭瘡鍊婦SP Slice鍙互鍩�(zh铆)琛屼箻娉曠疮鍔犻亱绠�锛岄潪甯搁仼鍚堟暩(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�銆�
銆�銆�3. 澶у閲廈lock RAM锛氳兘澶犳敮鎸佸京闆滅殑瀛樺劜闇�姹�锛屼緥濡傜珐瀛樻垨鏌ユ壘琛�銆�
銆�銆�4. 鏀寔澶氱ó閰嶇疆妯″紡锛氬寘鎷緸涓茶EEPROM鍔犺級閰嶇疆鏁�(sh霉)鎿�(j霉)鎴栬�呴�氶亷JTAG鎺ュ彛閫茶瑾�(di脿o)瑭�銆�
銆�銆�5. 鍏�(n猫i)缃檪閻樼鐞嗘ā濉婏細鏀寔PLL鍜孌LL鍔熻兘锛屾彁渚涢潏娲荤殑鏅傞悩鍒嗛厤鑸囩浉浣嶈(di脿o)鏁�銆�
銆�銆�6. 浣庡姛鑰楄ō(sh猫)瑷堬細鍦ㄤ繚璀夋�ц兘鐨勫悓鏅傜洝鍙兘娓涘皯鑳借��銆�
銆�銆�7. 鍙潬鎬ч珮锛氶仼鐢ㄤ簬鎯″姡鐠�(hu谩n)澧冧笅鐨勯棞(gu膩n)閸典换鍕欑郴绲�(t菕ng)闁嬬櫦(f膩)銆�
銆�銆�8. 寤ｆ硾鐨勬噳鐢ㄥ牬鏅敮鎸侊細鐒¤珫鏄�氫俊鍗�(xi茅)璀版⿱鎺ラ倓鏄鏅傝闋绘祦铏曠悊鍧囪兘鍕濅换銆�
XC4VLX60-11FFG1148I閬╃敤浜庝互涓嬪吀鍨嬫噳鐢ㄥ牬鏅細
銆�銆�1. 閫氫俊瑷�(sh猫)鍌欙細
銆�銆� - 鍩虹珯鎺у埗鍣�
銆�銆� - 璺敱鍣ㄨ垏浜ゆ彌姗�
銆�銆�2. 鍦栧儚铏曠悊锛�
銆�銆� - 瀵︽檪瑕栭牷绶ㄧ⒓瑙ｇ⒓
銆�銆� - 閱�(y墨)鐧傚奖鍍忓垎鏋�
銆�銆�3. 杌嶄簨鑸囪埅绌鸿埅澶╋細
銆�銆� - 灏庤埅绯荤当(t菕ng)
銆�銆� - 闆烽仈淇¤櫉铏曠悊
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細
銆�銆� - 閬嬪嫊鎺у埗
銆�銆� - 鏁�(sh霉)鎿�(j霉)閲囬泦鑸囩洠(ji膩n)鎺�
銆�銆�5. 娓│娓噺锛�
銆�銆� - 绀烘尝鍣ㄨЦ鐧�(f膩)閭忚集
銆�銆� - 鑷嫊娓│瑷�(sh猫)鍌欎腑鐨勫崝(xi茅)璀拌В鏋�
銆�銆�姝ゅ锛岀敱浜庡叾鍑鸿壊鐨勬�ц兘鍜屽彲闈犳��锛岄�欐FPGA閭勮寤ｆ硾鐢ㄤ簬绉戠爺瀵﹂骞宠嚭鎼缓浠ュ強鍘熷瀷椹楄瓑鐠�(hu谩n)澧冧腑銆�
XC4VLX60-10FFG1148I
銆�銆�XC4VLX60-12FFG1148I
