鏅傞枔锛�2022/10/25 15:29:29
闁辫畝锛�611
鐢�(ch菐n)鍝佸瀷铏� | XC4VLX40-10FFG668I |
鎻忚堪 | 闆嗘垚闆昏矾FPGA 448 I / O 668FCBGA |
鍒嗛 | 鎴愰浕璺�(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢�(ch菐n)鍝佸瀷铏� | XC4VLX40-10FFG668I |
鎻忚堪 | 闆嗘垚闆昏矾FPGA 448 I / O 668FCBGA |
鍒嗛 | 鎴愰浕璺�(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | Xilinx鍏徃 |
绯诲垪 | Virtex?-4LX |
鎵撳寘 | 鎵樼洡 |
闆朵欢鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 1.14V1.26V |
宸ヤ綔婧害 | -40掳C100掳C(TJ) |
鍖呰/绠� | 668-BBGA锛孎(xi脿n)CBGA |
渚涙噳鍟嗚ō鍌欏寘瑁� | 668-FCBGA(27x27) |
鍩烘湰闆朵欢铏� | XC4VLX40 |
Virtex-4LX锛氶珮鎬ц兘閭忚集鎳夌敤瑙ｆ焙鏂规
Xesium鏅傞悩鎶�琛�
鏁�(sh霉)瀛楁檪閻樼鐞嗗櫒(DCM)妯″
闄勫姞鐨勭浉浣嶅尮閰嶆檪閻樺垎闋诲櫒(PMCD)
宸垎鍏ㄥ眬鏅傞悩
XtremeDSPSlice
18x18锛屼簩閫插埗瑁滅⒓锛屽付绗﹁櫉涔樻硶鍣�
鍙伕鐨勭閬撻殠娈�
鍏�(n猫i)缃疮鍔犲櫒(48浣�)鍜屽姞娉曞櫒/娓涙硶鍣�
鏅鸿兘RAM鍏�(n猫i)瀛樺堡娆＄祼妲�
鍒嗗竷寮廟AM
闆欑鍙�18KbitRAM濉娐峰彲閬哥殑绠＄窔绱毬峰彲閬哥殑鍙法绋婩IFO閭忚集鑷嫊灏嘡AM淇¤櫉閲嶆柊鏄犲皠鐐篎IFO淇¤櫉
楂橀�熷瓨鍎插櫒鎺ュ彛鏀寔DDR鍜孌DR-2SDRAM锛孮DR-II鍜孯LDRAM-II
SelectIO鎶�琛�
1.5V鑷�3.3VI/O鎿嶄綔
鍏�(n猫i)缃瓹hipSync婧愬悓姝ユ妧琛�
鏁�(sh霉)鎺ч樆鎶�(DCI)鏈夋簮绲傜
绱扮矑搴︾殑I/O閵�琛屾キ(y猫)鍕�(鍦ㄤ竴鍊嬮妧琛屼腑閰嶇疆)
闈堟椿鐨勯倧杓硣婧�
瀹夊叏鑺墖AES浣嶆祦鍔犲瘑
90nm閵匔MOS宸ヨ棟
1.2V鏍稿績闆诲
鍊掕鑺墖灏佽锛屽寘鎷劇閴涘皝瑁濋伕鎿�
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎姝愮洘RoHS | 鏄� |
鐙�鎱�(t脿i) | 娲绘�� |
鏈�澶ф檪閻橀牷鐜� | 1028.0鍏嗚但 |
JESD-30浠ｇ⒓ | S-PBGA-B668 |
JESD-609浠ｇ⒓ | e1 |
绺絉AM浣� | 1769472 |
CLB鏁�(sh霉)閲� | 4608.0 |
杓稿叆鏁�(sh霉)閲� | 448.0 |
閭忚集鍠厓鏁�(sh霉) | 41472.0 |
杓稿嚭鏁�(sh霉)閲� | 448.0 |
绔瓙鏁�(sh霉) | 668 |
绲勭箶 | 4608 CLBS |
宄板�煎洖娴佹韩搴�(鈩�) | 245 |
搴ч珮 | 2.85姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲妯欑ū | 1.2浼� |
鏈�灏忎緵闆婚浕澹� | 1.14浼� |
鏈�澶ч浕婧愰浕澹� | 1.26浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛� | CMOS |
绲傜瀹屾垚 | 閷�/閵�/閵�(Sn95.5Ag4.0Cu0.5) |
绲傜琛ㄦ牸 | 鐞� |
绔瓙闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴︽渶澶у��(绉�) | 30 |
闀峰害 | 27.0姣背 |
瀵害 | 27.0姣背 |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呰绛夋晥浠ｇ⒓ | BGA668,26X26,40 |
鍖呰褰㈢媭 | 鍥涙柟褰� |
鍖呰褰㈠紡 | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 鐒￠墰FBGA-668 |
