XC4VLX40-10FFG668C 鏅�(sh铆)闁擄細2022/10/26 10:04:43 闁辫畝锛�575

鐢�(ch菐n)鍝佸瀷铏�(h脿o)	XC4VLX40-10FFG668C
鎻忚堪	IC FPGA 448 I/O 668FCBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)

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鐢�(ch菐n)鍝佸瀷铏�(h脿o)	XC4VLX40-10FFG668C
鎻忚堪	IC FPGA 448 I/O 668FCBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)
鐢熺敘(ch菐n)寤犲	Xilinx鍏徃
绯诲垪	Virtex?-4 LX
閮ㄥ垎鐙€鎱�(t脿i)	娲绘€�
闆诲-闆绘簮	1.14V~1.26V
宸ヤ綔婧害	0掳C~85掳C(TJ)
鍖�/绠�	668-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘	668-FCBGA(27x27)
鍩虹(ch菙)閮ㄤ欢铏�(h脿o)	XC4VLX40

鐗规€�

Virtex-4 LX锛氶珮鎬ц兘閭忚集鎳�(y墨ng)鐢ㄨВ姹烘柟妗�

Xesium鏅�(sh铆)閻樻妧琛�(sh霉)

鏁�(sh霉)瀛楁檪(sh铆)閻樼鐞嗗櫒(DCM)濉�

闄勫姞鐨勭浉浣嶅尮閰嶆檪(sh铆)閻樺垎闋诲櫒(PMCD)

宸垎鍏ㄧ悆鏅�(sh铆)閻�

XtremeDSP鍒囩墖

18 x 18锛屼簩閫�(j矛n)鍒惰(b菙)纰�锛屽付绗﹁櫉(h脿o)涔樻暩(sh霉)

鍙伕鐨勭閬撻殠娈�

鍏�(n猫i)缃疮鍔犲櫒(48浣�)鍜屽姞娉曞櫒/娓涙硶鍣�

鏅鸿兘RAM鍏�(n猫i)瀛樺堡娆＄祼(ji茅)妲�(g貌u)

鍒嗗竷寮廟AM

闆欑鍙�18-Kbit RAM妯″路鍙伕娴佹按绶氱礆(j铆)路鍙伕鐨勫彲绶ㄧ▼FIFO閭忚集鑷嫊(d貌ng)灏嘡AM淇¤櫉(h脿o)閲嶆柊鏄犲皠鐐篎IFO淇¤櫉(h脿o)

楂橀€熷瓨鍎�(ch菙)鍣ㄦ帴鍙ｆ敮鎸丏DR鍜孌DR-2 SDRAM锛孮DR-II鍜孯LDRAM-II銆�

SelectIO鎶€琛�(sh霉)

1.5V鑷�3.3VI / O鎿嶄綔

鍏�(n猫i)缃瓹hipSync婧愬悓姝ユ妧琛�(sh霉)

鏁�(sh霉)瀛楁帶鍒堕樆鎶�(DCI)鏈夋簮绲傜

绮剧窗(x矛)鐨処 / O閵€琛屾キ(y猫)鍕�(w霉)(鍦ㄤ竴瀹堕妧琛岄厤缃�)

闈堟椿鐨勯倧杓硣婧�

瀹夊叏鑺墖AES姣旂壒娴佸姞瀵�

90 nm閵匔MOS宸ヨ棟

1.2V鏍稿績闆诲

鍊掕鑺墖灏佽鍖呮嫭鐒�(w煤)閴涘皝瑁濋伕鎿�

鍙冩暩(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪
绗﹀悎REACH妯�(bi膩o)婧�(zh菙n)	鏄�
绗﹀悎姝愮洘RoHS妯�(bi膩o)婧�(zh菙n)	鏄�
鐙€鎱�(t脿i)	娲绘€�
鏅�(sh铆)閻橀牷鐜�-鏈€澶у€�	1028.0 MHz
JESD-30浠ｇ⒓	S-PBGA-B668
JESD-609浠ｇ⒓	E1
绺絉AM浣嶆暩(sh霉)	1769472
CLB鏁�(sh霉)閲�	4608.0
杓稿叆鏁�(sh霉)閲�	448.0
閭忚集鍠厓鐨勬暩(sh霉)	41472.0
杓稿嚭鏁�(sh霉)閲�	448.0
绲傜鏁�(sh霉)閲�	668
宸ヤ綔婧害-鏈€灏忓€�	0鈩�
宸ヤ綔婧害-鏈€楂�	85鈩�
绲勭箶	4608 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	245
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
鍧愬Э楂樺害-鏈€澶�	2.85姣背
瀛愰鍒�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪
闆绘簮闆诲	1.2 V
闆绘簮闆诲-鏈€灏忓€�	1.14 V
闆绘簮闆诲-鏈€澶у€�	1.26 V
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆(j铆)	鍏朵粬
绲傜瀹屾垚	閷�/閵€/閵�(Sn95.5Ag4.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绲傜闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅�(sh铆)闁揁宄板€煎洖娴佹韩搴�-鏈€澶у€�(s)	涓夊崄
闀�(zh菐ng)搴�	27.0姣背
瀵害	27.0姣背
鍖呰楂旀潗鏂�	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰９浠ｇ⒓	BGA
鍖呯瓑鍍�(ji脿)浠ｇ⒓	BGA668,26X26,40
鍖呰褰㈢媭	寤ｅ牬(ch菐ng)
鍖呰棰�(f膿ng)鏍�	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾�(shu艒)鏄�	鐒�(w煤)閴涳紝F(xi脿n)BGA-668