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鎮ㄥソ锛屾杩庝締鍒扮董搴�(k霉)闆诲瓙甯傚牬(ch菐ng)缍�(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺(c猫)

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩�(g貌u)缍�(w菐ng) > IC鐧剧 > XC4VLX15-10SFG363I

XC4VLX15-10SFG363I 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2022/10/26 11:10:17 鏌ョ湅 闁辫畝锛�1093

鐢�(ch菐n)鍝佸瀷铏�(h脿o)

XC4VLX15-10SFG363I

鎻忚堪

闆嗘垚闆昏矾FPGA 240 I / O 363FCBGA

鍒嗛

闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)

姒傝堪

鐢�(ch菐n)鍝佸瀷铏�(h脿o)

XC4VLX15-10SFG363I

鎻忚堪

闆嗘垚闆昏矾FPGA 240 I / O 363FCBGA

鍒嗛

闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)

鍒堕�犲晢

Xilinx鍏徃

绯诲垪

Virtex?-4LX

鎵撳寘

鎵樼洡

闆诲-闆绘簮

1.14V1.26V

宸ヤ綔婧害

-40掳C100掳C(TJ)

鍖呰/绠�

363-FBGA锛孎(xi脿n)CBGA

渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�

363-FCBGA(17x17)

鍩烘湰闆朵欢铏�(h脿o)

XC4VLX15

鍙冩暩(sh霉)

鍒堕�犲晢鍖呰瑾槑

鐒￠墰FBGA-363

绗﹀悎姝愮洘RoHS

鏄�

鐙�鎱�(t脿i)

娲绘��

鍙法绋嬮倧杓鍨�

鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪

鏈�澶ф檪(sh铆)閻橀牷鐜�

1028.0鍏嗚但

JESD-30浠ｇ⒓

S-PBGA-B363

JESD-609浠ｇ⒓

e1

绺絉AM浣�

884736

CLB鏁�(sh霉)閲�

1536.0

杓稿叆鏁�(sh霉)閲�

240.0

閭忚集鍠厓鏁�(sh霉)

13824.0

杓稿嚭鏁�(sh霉)閲�

240.0

绔瓙鏁�(sh霉)

363

绲勭箶

1536 CLBS

鍖呰涓婚珨鏉愭枡

濉戞枡/鐠�(hu谩n)姘фü鑴�

鍖呰浠ｇ⒓

FBGA

鍖呰绛夋晥浠ｇ⒓

BGA363,20X20,32

鍖呰褰㈢媭

鍥涙柟褰�

鍖呰褰㈠紡

缍�(w菐ng)鏍兼帓鍒楋紝绮剧窗(x矛)闁撹窛

宄板�煎洖娴佹韩搴�(鈩�)

260

搴ч珮

1.99姣背

瀛愰鍒�

鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪

闆绘簮闆诲妯�(bi膩o)绋�

1.2浼�

鏈�灏忎緵闆婚浕澹�

1.14浼�

鏈�澶ч浕婧愰浕澹�

1.26浼�

瀹夎椤炲瀷

琛ㄩ潰璨艰

鎶�琛�(sh霉)

CMOS

绲傜瀹屾垚

閷�/閵�/閵�(Sn95.5Ag4.0Cu0.5)

绲傜琛ㄦ牸

鐞�

绔瓙闁撹窛

0.8姣背

绲傜浣嶇疆

搴曢儴

鏅�(sh铆)闁揁宄板�煎洖娴佹韩搴�-鏈�澶у��(绉�)

30

闀�(zh菐ng)搴�

17.0姣背

瀵害

17.0姣背

寮曡叧鍦栬垏鍔熻兘

xc4vlx15-10sfg363i鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�(h脿o)
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉(h脿o)
  • 瑭㈠児(ji脿)

xc4vlx15-10sfg363i鍙冩暩(sh霉)

  • 妯�(bi膩o)婧�(zh菙n)鍖呰90
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛�
  • 绯诲垪Virtex®-4 LX
  • LAB/CLB鏁�(sh霉)1536
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)13824
  • RAM 浣嶇附瑷�(j矛)884736
  • 杓稿叆/杓稿嚭鏁�(sh霉)240
  • 闁�鏁�(sh霉)-
  • 闆绘簮闆诲1.14 V ~ 1.26 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害-40°C ~ 100°C
  • 灏佽/澶栨363-FBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�363-FCBGA锛�17x17锛�