XC4VLX100-10FFG1148I 鏅傞枔锛�2022/10/26 11:27:31 闁辫畝锛�784

鐢�(ch菐n)鍝佸瀷铏焁C4VLX100-10FFG1148I鎻忚堪 IC FPGA 768 I/O 1148FCBGA鍒嗛闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)

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鐢�(ch菐n)鍝佸瀷铏焁C4VLX100-10FFG1148I鎻忚堪 IC FPGA 768 I/O 1148FCBGA鍒嗛闆嗘垚闆昏矾(IC)锛屽祵鍏� 寮廎PGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)鐢熺敘(ch菐n)寤犲Xilinx鍏徃绯诲垪Virtex?-4 LX閮ㄥ垎鐙€鎱�(t脿i)娲绘€ч浕澹�-闆绘簮1.14V~1.26V宸ヤ綔婧害-40掳C~100掳C(TJ)鍖�/绠�1148-BBGA锛孎(xi脿n)CBGA渚涙噳鍟嗚ō(sh猫)鍌欏寘1148-FCPBGA(35x35)鍩虹(ch菙)閮ㄤ欢铏焁C4VLX100

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Xesium鏅傞悩鎶€琛�(sh霉)

鏁�(sh霉)瀛楁檪閻樼鐞嗗櫒(DCM)濉�

闄勫姞鐨勭浉浣嶅尮閰嶆檪閻樺垎闋诲櫒(PMCD)

宸垎鍏ㄧ悆鏅傞悩

XtremeDSP鍒囩墖

18 x 18锛屼簩閫插埗瑁滅⒓锛屽付绗﹁櫉涔樻暩(sh霉)

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鍏�(n猫i)缃疮鍔犲櫒(48浣�)鍜屽姞娉曞櫒/娓涙硶鍣�

鏅鸿兘RAM鍏�(n猫i)瀛樺堡娆＄祼(ji茅)妲�(g貌u)

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绗﹀悎REACH妯欐簴	鏄�
绗﹀悎姝愮洘RoHS妯欐簴	鏄�
鐙€鎱�(t脿i)	娲绘€�
鏅傞悩闋荤巼-鏈€澶у€�	1028.0 MHz
JESD-30浠ｇ⒓	S-PBGA-B1148
JESD-609浠ｇ⒓	E1
绺絉AM浣嶆暩(sh霉)	4423680
CLB鏁�(sh霉)閲�	12288.0
杓稿叆鏁�(sh霉)閲�	768.0
閭忚集鍠厓鐨勬暩(sh霉)閲�	110592.0
杓稿嚭鏁�(sh霉)閲�	768.0
绲傜鏁�(sh霉)閲�	1148
绲勭箶	12288 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	245
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闆绘簮闆诲-鏈€灏忓€�	1.14 V
闆绘簮闆诲-鏈€澶у€�	1.26 V
瀹夎椤炲瀷	琛ㄩ潰璨艰
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绲傜琛ㄦ牸	鐞�
绲傜闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅傞枔@宄板€煎洖娴佹韩搴�-鏈€澶у€�	涓夊崄
闀峰害	35.0姣背
瀵害	35.0姣背
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鍖呰９浠ｇ⒓	BGA
鍖呯瓑鍍逛唬纰�	BGA1148,34X34,40
鍖呰褰㈢媭	寤ｅ牬
鍖呰棰ㄦ牸	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	鐒￠墰锛孎(xi脿n)BGA-1148