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鎮ㄥソ锛屾杩庝締(l谩i)鍒扮董搴�(k霉)闆诲瓙甯傚牬(ch菐ng)缍�(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺(c猫)

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩�(g貌u)缍�(w菐ng) > IC鐧剧 > XC4VFX12-11FFG668C

XC4VFX12-11FFG668C 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2022/11/4 16:59:36 鏌ョ湅 闁辫畝锛�611

鐢�(ch菐n)鍝佸瀷铏�(h脿o)

XC4VFX12-11FFG668C

鎻忚堪

闆嗘垚闆昏矾FPGA 320 I/O 668FCBGA

鍒嗛(l猫i)

闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪)

姒傝堪

鐢�(ch菐n)鍝佸瀷铏�(h脿o)

XC4VFX12-11FFG668C

鎻忚堪

闆嗘垚闆昏矾FPGA 320 I/O 668FCBGA

鍒嗛(l猫i)

闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪)

鍒堕�犲晢

Xilinx鍏徃

绯诲垪

Virtex?-4FX

闆朵欢鐙�鎱�(t脿i)

娲绘��

闆诲-闆绘簮

1.14V1.26V

宸ヤ綔婧害

0掳C85掳C(TJ)

鍖呰/绠�

668-BBGA锛孎(xi脿n)CBGA

渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�

668-FCBGA(27x27)

鍩烘湰闆朵欢铏�(h脿o)

XC4VFX12

鐗规��

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    XtremeDSPSlice

    18 x 18锛屼簩閫�(j矛n)鍒惰(b菙)纰�锛屽付绗﹁櫉(h脿o)涔樻硶鍣�

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    澶氬��(g猫)涓夋厠(t脿i)浠ュお缍�(w菐ng)MAC [鍍匜X]


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鍙法绋嬮倧杓(l猫i)鍨�

鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪

绗﹀悎REACH

鏄�

绗﹀悎姝愮洘RoHS

鏄�

鐙�鎱�(t脿i)

娲绘��

鏈�澶ф檪(sh铆)閻橀牷鐜�

1181.0鍏嗚但

JESD-30浠ｇ⒓

S-PBGA-B668

JESD-609浠ｇ⒓

1铏�(h脿o)

绺絉AM浣�

663552

CLB鏁�(sh霉)閲�

1368.0

杓稿叆鏁�(sh霉)閲�

320.0

閭忚集鍠厓鏁�(sh霉)

12312.0

杓稿嚭鏁�(sh霉)閲�

320.0

绔瓙鏁�(sh霉)

668

鏈�浣庡伐浣滄韩搴�

0鈩�

鏈�楂樺伐浣滄韩搴�

85鈩�

绲勭箶

1368 CLBS

宄板�煎洖娴佹韩搴�(鈩�)

245

璩囨牸鐙�鎱�(t脿i)

涓嶅悎鏍�

搴ч珮

2.85姣背

瀛愰(l猫i)鍒�

鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪

闆绘簮闆诲妯�(bi膩o)绋�(ch膿ng)

1.2浼�

鏈�灏忎緵闆婚浕澹�

1.14浼�

鏈�澶ч浕婧愰浕澹�

1.26浼�

瀹夎椤�(l猫i)鍨�

琛ㄩ潰璨艰

鎶�琛�(sh霉)

CMOS

婧害绛夌礆(j铆)

鍏朵粬

绲傜瀹屾垚

閷�/閵�/閵�(Sn95.5Ag4.0Cu0.5)

绲傜琛ㄦ牸

鐞�

绔瓙闁撹窛

1.0姣背

绲傜浣嶇疆

搴曢儴

鏅�(sh铆)闁揁宄板�煎洖娴佹韩搴︽渶澶у��(绉�)

30

闀�(zh菐ng)搴�

27.0姣背

瀵害

27.0姣背

鍖呰涓婚珨鏉愭枡

濉戞枡/鐠�(hu谩n)姘фü(sh霉)鑴�

鍖呰浠ｇ⒓

BGA

鍖呰绛夋晥浠ｇ⒓

BGA668,26X26,40

鍖呰褰㈢媭

寤ｅ牬(ch菐ng)

鍖呰褰㈠紡

缍�(w菐ng)鏍奸櫍鍒�

鍒堕�犲晢鍖呰瑾�(shu艒)鏄�

鐒�(w煤)閴汧BGA-668

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xc4vfx12-11ffg668c鍙冩暩(sh霉)

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  • 椤�(l猫i)鍒�闆嗘垚闆昏矾 (IC)
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  • 绯诲垪Virtex®-4 FX
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  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)12312
  • RAM 浣嶇附瑷�(j矛)663552
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  • 宸ヤ綔婧害0°C ~ 85°C
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  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�668-FCBGA
  • 閰嶇敤HW-V4-ML403-UNI-G-ND - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400-ND - BOARD DEV VIRTEX 4 FF668