鏅傞枔锛�2023/8/4 17:38:35
闁辫畝锛�595
鐢㈠搧鍨嬭櫉 | XC4VFX12-10SF363I |
鎻忚堪 | IC FPGA 240 I/O 363FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢熺敘寤犲 | Xilinx鍏徃 |
绯诲垪 | Virtex?-4 FX |
閮ㄥ垎鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 1.14V~1.26V |
宸ヤ綔婧害 | -40掳C~100掳C(TJ) |
鍖�/绠� | 363-FBGA锛孎(xi脿n)CBGA |
渚涙噳鍟嗚ō鍌欏寘 | 363-FCBGA(17x17) |
鍩虹閮ㄤ欢铏� | XC4VFX12 |
XC4VFX12-10SF363I
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎REACH妯欐簴 | 鏄� |
鐙�鎱�(t脿i) | 娲绘�� |
鏅傞悩闋荤巼-鏈�澶у�� | 1028.0 MHz |
JESD-30浠ｇ⒓ | S-PBGA-B363 |
JESD-609浠ｇ⒓ | E0 |
绺絉AM浣嶆暩(sh霉) | 663552 |
CLB鏁�(sh霉)閲� | 1368.0 |
杓稿叆鏁�(sh霉)閲� | 240.0 |
閭忚集鍠厓鐨勬暩(sh霉)閲� | 12312.0 |
杓稿嚭鏁�(sh霉)閲� | 240.0 |
绲傜鏁�(sh霉)閲� | 363 |
绲勭箶 | 1368 CLBS |
宄板�煎洖娴佹韩搴�(鈩�) | 225 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
鍧愬Э楂樺害-鏈�澶� | 1.99姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲 | 1.2 V |
闆绘簮闆诲-鏈�灏忓�� | 1.14 V |
闆绘簮闆诲-鏈�澶у�� | 1.26 V |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛� | CMOS |
绲傜瀹屾垚 | 閷�/閴�(Sn63Pb37) |
绲傜琛ㄦ牸 | 鐞� |
绲傜闁撹窛 | 0.8姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶у�� | 涓夊崄 |
闀峰害 | 17.0姣背 |
瀵害 | 17.0姣背 |
鍖呰楂旀潗鏂� | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰９浠ｇ⒓ | FBGA |
鍖呯瓑鍍逛唬纰� | BGA363,20X20,32 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰棰ㄦ牸 | 缍�(w菐ng)鏍奸櫍鍒�锛岀簿绱伴枔璺� |
鍒堕�犲晢鍖呰瑾槑 | FBGA-363 |
鐒￠墰鐙�鎱�(t脿i)/RoHS鐙�鎱�(t脿i) | 鍖呭惈閴�/RoHS涓嶅悎瑕�(gu墨) |
婵曞害鏁忔劅搴︾瓑绱�(MSL) | 4(72灏忔檪) |
?Virtex-4 FX锛氶仼鐢ㄤ簬宓屽叆寮忓钩鑷烘噳鐢ㄧ殑楂樻�ц兘锛屽叏鍔熻兘瑙ｆ焙鏂规
?Xesium?鏅傞悩鎶�琛�
銆傛暩(sh霉)瀛楁檪閻樼鐞嗗櫒(DCM)濉�
銆傞檮鍔犵殑鐩镐綅鍖归厤鏅傞悩鍒嗛牷鍣�(PMCD)
銆傚樊鍒嗗叏鐞冩檪閻�
?XtremeDSP?鍒囩墖
銆�18 x 18锛屼簩閫插埗瑁滅⒓锛屽付绗﹁櫉涔樻暩(sh霉)
?锛熻泧x鐨勭閬撻殠娈�
銆傚収缃疮鍔犲櫒(48浣�)鍜屽姞娉曞櫒/娓涙硶鍣�
?鏅鸿兘RAM鍏у瓨灞ゆ绲愭
銆傚垎甯冨紡RAM
銆傞洐绔彛18-Kbit RAM妯″路鍙伕娴佹按绶氱礆路鍙伕鐨勫彲绶ㄧ▼FIFO閭忚集鑷嫊灏嘡AM淇¤櫉閲嶆柊鏄犲皠鐐篎IFO淇¤櫉
銆傞珮閫熷瓨鍎插櫒鎺ュ彛鏀寔DDR鍜孌DR-2 SDRAM锛孮DR-II鍜孯LDRAM-II銆�
?SelectIO?鎶�琛�
銆�1.5V鑷�3.3VI / O鎿嶄綔
銆傚収缃瓹hipSync?婧愬悓姝ユ妧琛�
銆傛暩(sh霉)瀛楁帶鍒堕樆鎶�(DCI)鏈夋簮绲傜
銆傜簿绱扮殑I / O閵�琛屾キ(y猫)鍕�(鍦ㄤ竴瀹堕妧琛岄厤缃�)
?闈堟椿鐨勯倧杓硣婧�
?瀹夊叏鑺墖AES姣旂壒娴佸姞瀵�
?90 nm閵匔MOS宸ヨ棟
?1.2V鏍稿績闆诲
?鍊掕鑺墖灏佽鍖呮嫭鐒￠墰灏佽閬告搰
?RocketIO?622 Mb / s鑷�6.5 Gb / s澶氬崈鍏嗕綅鏀剁櫦(f膩)鍣�(MGT)[鍍呴檺FX]
?IBM PowerPC RISC铏曠悊鍣ㄦ牳蹇僛鍍呴檺FX]
銆侾owerPC 405(PPC405)鏍稿績
銆傝紨鍔╄檿鐞嗗櫒鍠厓鎺ュ彛(鐢ㄦ埗鍗�(xi茅)铏曠悊鍣�)
?澶氬�嬩笁鎱�(t脿i)浠ュお缍�(w菐ng)MAC [鍍呴檺FX]
XC4VFX12-10SF363I绗﹁櫉
XC4VFX12-10SF363I鑵冲嵃
