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銆�銆�瑭� FPGA 鍏ч儴闆嗘垚浜嗚睈瀵岀殑璩囨簮锛屼緥濡傚祵鍏ュ紡濉� RAM銆丏SP Slice 鍜岄珮閫熸敹鐧�(f膩)鍣ㄧ瓑锛岀偤瑷▓鑰呮彁渚涗簡妤靛ぇ鐨勯潏娲绘�у拰寮峰ぇ鐨勫姛鑳芥摯灞曡兘鍔�銆�
閭忚集鍠厓锛�18,432
銆�銆�閰嶇疆瀛樺劜浣嶏細绱� 1,800 钀�
銆�銆�宓屽叆寮忓 RAM锛�768 KB
銆�銆�DSP Slice 鏁搁噺锛�96
銆�銆�I/O 寮曡叧鏁搁噺锛�336
銆�銆�宸ヤ綔闆诲锛�1.2V 鏍稿績闆诲 / 3.3V I/O 闆诲
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銆�銆�灏佽椤炲瀷锛欳SG484
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XC3SD1800A 鎻愪緵浜嗘サ楂樼殑閭忚集瀵嗗害鍜屾�ц兘锛屽悓鏅傚叿鍌欎互涓嬬壒榛烇細
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XC3SD1800A-5CSG484C 鐨勫吀鍨嬫噳鐢ㄥ牬鏅寘鎷絾涓嶉檺浜庝互涓嬮牁鍩燂細
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XC3SD1800A-4CSG484C
銆�銆�XC3SD1800A-5FGG484C
銆�銆�XC3SD1800A-4FGG484C
