鏅傞枔锛�2022/11/2 16:05:32
闁辫畝锛�817
鐢�(ch菐n)鍝佸瀷铏� | XC2VP4-5FGG256I |
鎻忚堪 | IC FPGA 140 I/O 256FBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢�(ch菐n)鍝佸瀷铏� | XC2VP4-5FGG256I |
鎻忚堪 | IC FPGA 140 I/O 256FBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | Xilinx鍏徃 |
绯诲垪 | Virtex?-IIPro |
闆朵欢鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 1.425V1.575V |
宸ヤ綔婧害 | -40掳C100掳C(TJ) |
鍖呰/绠� | 256-BGA |
渚涙噳鍟嗚ō鍌欏寘瑁� | 256-FBGA(17x17) |
鍩烘湰闆朵欢铏� | XC2VP4 |
楂樻�ц兘骞宠嚭FPGA瑙ｆ焙鏂规锛屽寘鎷�
澶氶仈浜屽崄鍊婻ocketIO鎴朢ocketIO X宓屽叆寮忓鍗冨厗浣嶆敹鐧�(f膩)鍣�(MGT)
澶氶仈鍏╁�婭BM PowerPCRISC铏曠悊鍣ㄦā濉�
鍩轰簬Virtex-II骞宠嚭FPGA鎶�琛�(sh霉)
闈堟椿鐨勯倧杓硣婧�
鍩轰簬SRAM鐨勭郴绲�(t菕ng)鍏�(n猫i)閰嶇疆
涓诲嫊浜掗�ｆ妧琛�(sh霉)
SelectRAM+瀛樺劜鍣ㄥ堡娆＄祼(ji茅)妲�(g貌u)
灏堢敤鐨�18浣峹 18浣嶄箻娉曞櫒濉�
楂樻�ц兘鏅傞悩绠＄悊闆昏矾
SelectI / O-瓒呮妧琛�(sh霉)
XCITE鏁�(sh霉)鎺ч樆鎶�(DCI)I / O
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎REACH | 鏄� |
绗﹀悎姝愮洘RoHS | 鏄� |
鐙�鎱�(t脿i) | NRFND |
鏈�澶ф檪閻橀牷鐜� | 1050.0鍏嗚但 |
CLB-Max鐨勭祫鍚堝欢閬� | 0.36绱嶇 |
JESD-30浠ｇ⒓ | S-PBGA-B256 |
JESD-609浠ｇ⒓ | 1铏� |
绺絉AM浣� | 516096 |
CLB鏁�(sh霉)閲� | 752.0 |
杓稿叆鏁�(sh霉)閲� | 140.0 |
閭忚集鍠厓鏁�(sh霉) | 6768.0 |
杓稿嚭鏁�(sh霉)閲� | 140.0 |
绔瓙鏁�(sh霉) | 256 |
绲勭箶 | 752 CLBS |
宄板�煎洖娴佹韩搴�(鈩�) | 260 |
闆绘簮 | 1.5,1.5 / 3.3,2 / 2.5,2.5 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
搴ч珮 | 2.0姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲妯欑ū | 1.5浼� |
鏈�灏忎緵闆婚浕澹� | 1.425浼� |
鏈�澶ч浕婧愰浕澹� | 1.575浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
绲傜瀹屾垚 | 閷�/閵�/閵�(Sn95.5Ag4.0Cu0.5) |
绲傜琛ㄦ牸 | 鐞� |
绔瓙闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴︽渶澶у��(绉�) | 30 |
闀峰害 | 17.0姣背 |
瀵害 | 17.0姣背 |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呰绛夋晥浠ｇ⒓ | BGA256,16X16,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰褰㈠紡 | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 17 X 17 MM锛�1 MM闁撹窛锛岀劇閴涳紝MS-034AAF-1锛孎(xi脿n)BGA-256 |
