鏅傞枔锛�2022/11/2 16:05:51
闁辫畝锛�901
鐢�(ch菐n)鍝佸瀷铏� | XC2VP20-5FGG676I |
鎻忚堪 | IC FPGA 404 I/O 676FBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢�(ch菐n)鍝佸瀷铏� | XC2VP20-5FGG676I |
鎻忚堪 | IC FPGA 404 I/O 676FBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢熺敘(ch菐n)寤犲 | Xilinx鍏徃 |
绯诲垪 | Virtex?-II Pro |
閮ㄥ垎鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 1.425V~1.575V |
宸ヤ綔婧害 | -40掳C~100掳C(TJ) |
鍖�/绠� | 676-BGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘 | 676-FBGA(27x27) |
鍩虹(ch菙)閮ㄤ欢铏� | XC2VP20 |
楂樻�ц兘骞宠嚭FPGA瑙ｆ焙鏂规锛屽寘鎷�
澶氶仈20鍊婻ocketIO鎴朢ocketIO X宓屽叆寮忓鍗冨厗浣嶆敹鐧�(f膩)鍣�(MGT)
鏈�澶氬叐鍊婭BM PowerPCRISC铏曠悊鍣ㄥ
鍩轰簬Virtex-II骞宠嚭FPGA鎶�琛�(sh霉)
闈堟椿鐨勯倧杓硣婧�
鍩轰簬SRAM鐨勭郴绲�(t菕ng)鍏�(n猫i)閰嶇疆
鏈夋簮浜掗�ｆ妧琛�(sh霉)
SelectRAM+鍏�(n猫i)瀛樺堡娆＄祼(ji茅)妲�(g貌u)
灏堢敤鐨�18浣峹 18浣嶄箻娉曞櫒妯″
楂樻�ц兘鏅傞悩绠＄悊闆昏矾
SelectI / O-Ultra鎶�琛�(sh霉)
XCITE鏁�(sh霉)瀛楁帶鍒堕樆鎶�(DCI)I /O
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎REACH妯�(bi膩o)婧�(zh菙n) | 鏄� |
绗﹀悎姝愮洘RoHS妯�(bi膩o)婧�(zh菙n) | 鏄� |
鐙�鎱�(t脿i) | NRFND |
鏅傞悩闋荤巼-鏈�澶у�� | 1050.0 MHz |
CLB-Max鐨勭祫鍚堝欢閬� | 0.36 ns |
JESD-30浠ｇ⒓ | S-PBGA-B676 |
JESD-609浠ｇ⒓ | E1 |
绺絉AM浣嶆暩(sh霉) | 1622016 |
CLB鏁�(sh霉)閲� | 2320.0 |
杓稿叆鏁�(sh霉)閲� | 404.0 |
閭忚集鍠厓鐨勬暩(sh霉)閲� | 20880.0 |
杓稿嚭鏁�(sh霉)閲� | 404.0 |
绲傜鏁�(sh霉)閲� | 676 |
绲勭箶 | 2320 CLBS |
宄板�煎洖娴佹韩搴�(鈩�) | 250 |
闆绘簮 | 1.5,1.5 / 3.3,2 / 2.5,2.5 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
鍧愬Э楂樺害-鏈�澶� | 2.44姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲 | 1.5 V |
闆绘簮闆诲-鏈�灏忓�� | 1.425 V |
闆绘簮闆诲-鏈�澶у�� | 1.575 V |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
绲傜瀹屾垚 | 閷�/閵�/閵�(Sn95.5Ag4.0Cu0.5) |
绲傜琛ㄦ牸 | 鐞� |
绲傜闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶у��(s) | 涓夊崄 |
闀峰害 | 27.0姣背 |
瀵害 | 27.0姣背 |
鍖呰楂旀潗鏂� | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰９浠ｇ⒓ | BGA |
鍖呯瓑鍍逛唬纰� | BGA676,26X26,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰棰�(f膿ng)鏍� | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 26 X 26 MM锛�1 MM闁撹窛锛岀劇閴�锛孧S-034AAL-1锛孎(xi脿n)BGA-676 |
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