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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XC2V500-5FGG256I

XC2V500-5FGG256I 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2023/7/11 14:21:49 鏌ョ湅 闁辫畝锛�1030

鎻忚堪

XC2V500-5FGG256I鏄偤楂樻�ц兘寰炰綆瀵嗗害鍒伴珮瀵嗗害瑷�(sh猫)瑷堣�岄枊鐧�(f膩)鐨勫钩鑷篎PGA锛屽熀浜巐P鍏�(n猫i)鏍稿拰瀹氬埗妯″銆傝┎鍣ㄤ欢鐐洪浕淇�銆佺劇绶�銆佺恫(w菐ng)绲�(lu貌)銆佽闋诲拰DSP鎳�(y墨ng)鐢ㄦ彁渚涘畬鏁寸殑瑙ｆ焙鏂规锛屽寘鎷琍CI銆丩VDS鍜孌DR鎺ュ彛銆俋C2V500-5FGG256I閲囩敤0.15um/0.12umCMOS8灞ら噾灞伐钘濆拰Virtex-ll鏋舵(g貌u)閲濆皪楂橀�熷拰浣庡姛鑰楅�茶浜嗗劒(y艒u)鍖栫祼(ji茅)鍚堜簡寤ｆ硾鐨勯潏娲诲姛鑳藉拰楂橀仈1000钀�嬬郴绲�(t菕ng)闁�鐨勫ぇ鑼冨湇瀵嗗害锛屽寮蜂簡鍙法绋嬮倧杓ō(sh猫)瑷堣兘鍔涳紝鏄帺鑶滅法绋嬮杸闄ｅ垪鐨勫挤澶ф浛浠ｅ搧銆�

鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸瀷铏�

XC2V500-5FGG256I

鎻忚堪

闆嗘垚闆昏矾FPGA 172 I / O 256FBGA

鍒嗛

闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪)

鍒堕�犲晢

Xilinx鍏徃

绯诲垪

Virtex?-II

闆诲-闆绘簮

1.425V?1.575V

宸ヤ綔婧害

-40掳C?100掳C(TJ)

鍖呰/绠�

256-BGA

渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�

256-FBGA(17x17)

鍩烘湰闆朵欢铏�

XC2V500

鐢�(ch菐n)鍝佸湒鐗�

XC2V500-5FGG256I

XC2V500-5FGG256I

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鐢�(ch菐n)鍝佺ó椤�

FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪

鐢�(ch菐n)鍝�

Virtex-II

绯诲垪

XC2V500

鑷仼鎳�(y墨ng)閭忚集妯″-ALM

3072 ALM

宓屽叆寮忓収(n猫i)瀛�

576 kbit

杓稿叆/杓稿嚭绔暩(sh霉)閲�

172 I/O

宸ヤ綔闆绘簮闆诲

1.5 V

鏈�灏忓伐浣滄韩搴�

- 40鈩�

鏈�澶у伐浣滄韩搴�

+ 100鈩�

鏌垫サ鏁�(sh霉)閲�

500000

闁橀杸鏁�(sh霉)閲�

500000

閭忚集濉�(LAB)鐨勬暩(sh霉)閲�

768

瀵勫瓨鍣ㄦ暩(sh霉)

6144

鍒嗗竷寮廟AM

96 kbit

鍏�(n猫i)宓屽紡濉奟AM - EBR

576 kbit

鍖呰

鎵樼洡

瀹夎棰�(f膿ng)鏍�

SMD/SMT

灏佽/绠遍珨

FBGA-256

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

姘村垎鏁忔劅鎬ф按骞�(MSL)

3(168灏忔檪)

RoHS鎸囦护

鍚堣(gu墨)

CAD妯″瀷

XC2V500-5FGG256I绗﹁櫉

XC2V500-5FGG256I绗﹁櫉

XC2V500-5FGG256I鑵冲嵃

XC2V500-5FGG256I鑵冲嵃

灏佽

XC2V500-5FGG256I灏佽

XC2V500-5FGG256I灏佽

鏇夸唬鍨嬭櫉

鍨嬭櫉

鍒堕�犲晢

鍝佸悕

鎻忚堪

XC2V500-4FGG256C

璩介潏鎬�

FPGA鑺墖

500K Gates 6912 Cells 650MHz 0.15um Technology 1.5V 256Pin FBGA

XC2V500-4FGG256I

璩介潏鎬�

FPGA鑺墖

500K Gates 6912 Cells 650MHz 0.15um Technology 1.5V 256Pin FBGA

XC2V500-5FGG256C

璩介潏鎬�

FPGA鑺墖

500K Gates 6912 Cells 750MHz 0.15um Technology 1.5V 256Pin FBGA

xc2v500-5fgg256i鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xc2v500-5fgg256i鍦栫墖

xc2v500-5fgg256i

xc2v500-5fgg256i鍙冩暩(sh霉)

  • 妯欐簴鍖呰90
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛�
  • 绯诲垪Virtex®-II
  • LAB/CLB鏁�(sh霉)768
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)-
  • RAM 浣嶇附瑷�589824
  • 杓稿叆/杓稿嚭鏁�(sh霉)172
  • 闁�鏁�(sh霉)500000
  • 闆绘簮闆诲1.425 V ~ 1.575 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害-40°C ~ 100°C
  • 灏佽/澶栨256-BGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�256-FBGA锛�17x17锛�