鏅傞枔锛�2023/8/4 17:46:16
闁辫畝锛�693
鐢�(ch菐n)鍝佸瀷铏� | XC2V4000-4FF1152I |
鎻忚堪 | IC FPGA 824 I/O 1152FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢熺敘(ch菐n)寤犲 | Xilinx鍏徃 |
绯诲垪 | Virtex?-II |
閮ㄥ垎鐙�鎱�(t脿i) | 閬庢檪鐨� |
闆诲-闆绘簮 | 1.425V~1.575V |
宸ヤ綔婧害 | -40掳C~100掳C(TJ) |
鍖�/绠� | 1152-BBGA锛孎(xi脿n)CBGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘 | 1152-CFCBGA(35x35) |
鍩虹(ch菙)閮ㄤ欢铏� | XC2V4000 |
XC2V4000-4FF1152I
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
鐙�鎱�(t脿i) | 鍋滅敘(ch菐n) |
鏅傞悩闋荤巼-鏈�澶у�� | 650.0 MHz |
CLB-Max鐨勭祫鍚堝欢閬� | 0.44 ns |
JESD-30浠ｇ⒓ | S-PBGA-B1152 |
JESD-609浠ｇ⒓ | E0 |
绺絉AM浣嶆暩(sh霉) | 2211840 |
CLB鏁�(sh霉)閲� | 5760.0 |
绛夋晥闁�鏁�(sh霉) | 4000000.0 |
杓稿叆鏁�(sh霉)閲� | 824.0 |
閭忚集鍠厓鐨勬暩(sh霉)閲� | 51840.0 |
杓稿嚭鏁�(sh霉)閲� | 824.0 |
绲傜鏁�(sh霉)閲� | 1152 |
绲勭箶 | 5760 CLBS锛�4000000 GATES |
宄板�煎洖娴佹韩搴�(鈩�) | 225 |
闆绘簮 | 1.5,1.5 / 3.3,3.3 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
鍧愬Э楂樺害-鏈�澶� | 3.4姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲 | 1.5 V |
闆绘簮闆诲-鏈�灏忓�� | 1.425 V |
闆绘簮闆诲-鏈�澶у�� | 1.575 V |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
绲傜瀹屾垚 | 閷�/閴�(Sn63Pb37) |
绲傜琛ㄦ牸 | 鐞� |
绲傜闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶у��(s) | 涓夊崄 |
闀峰害 | 35.0姣背 |
瀵害 | 35.0姣背 |
鍖呰楂旀潗鏂� | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰９浠ｇ⒓ | BGA |
鍖呯瓑鍍逛唬纰� | BGA1152,34X34,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰棰�(f膿ng)鏍� | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 35 X 35 MM锛�1 MM闁撹窛锛孧S-034AAR-1锛岀炕杞�(zhu菐n)鑺墖锛孎(xi脿n)BGA-1152 |
鐒￠墰鐙�鎱�(t脿i)/RoHS鐙�鎱�(t脿i) | 鍖呭惈閴�/RoHS涓嶅悎瑕�(gu墨) |
婵曞害鏁忔劅搴︾瓑绱�(MSL) | 4(72灏忔檪) |
?妤�(y猫)鐣岄鍊嬪钩鑷篎PGA瑙ｆ焙鏂规
?IP娌夋蹈寮忔灦妲�(g貌u)
- 瀵嗗害寰�40K鍒�8M绯荤当(t菕ng)闁�
- 420 MHz鍏�(n猫i)閮ㄦ檪閻橀�熷害(楂樼礆鏁�(sh霉)鎿�(j霉))
- 840+ Mb / s I / O(楂樼礆鏁�(sh霉)鎿�(j霉))
?SelectRAM?鍏�(n猫i)瀛樺堡娆＄祼(ji茅)妲�(g貌u)
- 18 Kbit濉奡electRAM璩囨簮涓殑3 Mb闆欑鍙AM
- 楂橀仈1.5 Mb鐨勫垎甯冨紡SelectRAM璩囨簮
?澶栭儴瀛樺劜鍣ㄧ殑楂樻�ц兘鎺ュ彛
- DRAM鎺ュ彛
路SDR / DDR SDRAM
路缍�(w菐ng)绲�(lu貌)FCRAM
路娓涘皯寤堕伈DRAM
- SRAM鎺ュ彛
路SDR / DDR SRAM
路QDR?SRAM
- CAM鎺ュ彛
?绠楄(sh霉)鍑芥暩(sh霉)
- 灏堢敤鐨�18浣峹 18浣嶄箻娉曞櫒妯″
- 蹇�熷墠鐬绘壙杓夐倧杓張
?闈堟椿鐨勯倧杓硣婧�
- 鍏锋湁鏅傞悩浣胯兘鍔熻兘鐨勯珮閬�93,184鍊嬪収(n猫i)閮ㄥ瘎瀛樺櫒/閹栧瓨鍣�
- 澶氶仈93,184鍊嬫煡鎵捐〃(LUT)鎴栧彲绱氳伅(li谩n)鐨�16浣嶇Щ浣嶅瘎瀛樺櫒
- 瀵璺京(f霉)鐢ㄥ櫒鍜屽杓稿叆鍔熻兘鏀寔
- 姘村钩绱氳伅(li谩n)閺堝拰鐢�(ch菐n)鍝佺附鍜屾敮鎸�
- 鍏�(n猫i)閮ㄤ笁鎱�(t脿i)鍖祦
?楂樻�ц兘鏅傞悩绠＄悊闆昏矾
- 鏈�澶�12鍊婦CM(鏁�(sh霉)瀛楁檪閻樼鐞嗗櫒)妯″
路绮剧⒑鐨勬檪閻樺亸绉�
路闈堟椿鐨勯牷鐜囧悎鎴�
路楂樺垎杈ㄧ巼鐩哥Щ
- 16鍊嬪叏灞�鏅傞悩澶氳矾寰�(f霉)鐢ㄥ櫒绶╂矕鍣�
?鏈夋簮浜掗�ｆ妧琛�(sh霉)
- 绗洓浠ｅ垎娈佃矾鐢辩祼(ji茅)妲�(g貌u)
- 鍙爯(y霉)娓殑蹇�熻矾鐢卞欢閬�锛岀崹绔嬩簬鎵囧嚭
?SelectIO?-Ultra鎶�琛�(sh霉)
- 鏈�澶�1,108鍊嬬敤鎴禝 / O.
- 19鍊嬪柈绔拰6鍊嬪樊鍒嗘(bi膩o)婧�(zh菙n)
- 姣忓�婭 / O鍙法绋嬬亴闆绘祦(2 mA鑷�24 mA)
- 鏁�(sh霉)瀛楁帶鍒堕樆鎶�(DCI)I / O锛氱敤浜庡柈绔疘 / O妯�(bi膩o)婧�(zh菙n)鐨勭墖鍏�(n猫i)鍖归厤闆婚樆
- 3.3V鏅傚吋瀹筆CI-X(133 MHz鍜�66 MHz)
- 绗﹀悎PCI妯�(bi膩o)婧�(zh菙n)(66 MHz鍜�33 MHz)锛�3.3V
- 绗﹀悎CardBus妯�(bi膩o)婧�(zh菙n)(33 MHz)锛�3.3V
- 宸垎淇′护
路鍏锋湁闆绘祦妯″紡椹�(q奴)鍕曞櫒鐨�840 Mb / s浣庡宸垎淇¤櫉I / O(LVDS)
路绺界窔LVDS I / O.
路鍏锋湁鐣�(d膩ng)鍓嶉﹨(q奴)鍕曠▼搴忕珐娌栧崁(q奴)鐨勯杻闆绘暩(sh霉)鎿�(j霉)鍌宠几(LDT)I / O.
路浣庡姝ｇ櫦(f膩)灏勬サ鑰﹀悎閭忚集(LVPECL)I / O.
路鍏�(n猫i)缃瓺DR杓稿叆鍜岃几鍑哄瘎瀛樺櫒
- 灏堟湁鐨勯珮鎬ц兘SelectLink鎶�琛�(sh霉)
路楂樺付瀵暩(sh霉)鎿�(j霉)璺緫
路闆欏�嶆暩(sh霉)鎿�(j霉)閫熺巼(DDR)閺堟帴
路鍩轰簬Web鐨凥DL鐢熸垚鏂规硶
?鐢盭ilinx Foundation?鍜孉lliance Series?闁嬬櫦(f膩)绯荤当(t菕ng)鎻愪緵鏀寔
- 闆嗘垚鐨刅HDL鍜孷erilog瑷�(sh猫)瑷堟祦绋�
- 10M绯荤当(t菕ng)闁�瑷�(sh猫)瑷堢殑鍖法
- 浜掕伅(li谩n)缍�(w菐ng)鍦橀殜瑷�(sh猫)瑷�(ITD)宸ュ叿
?鍩轰簬SRAM鐨勭郴绲�(t菕ng)鍏�(n猫i)閰嶇疆
- 蹇�烻electMAP閰嶇疆
- 涓夐噸鏁�(sh霉)鎿�(j霉)鍔犲瘑妯�(bi膩o)婧�(zh菙n)(DES)瀹夊叏閬搁爡(姣旂壒娴佸姞瀵�)
- IEEE 1532鏀寔
- 閮ㄥ垎閲嶆柊閰嶇疆
- 鐒￠檺鍒剁殑鍙噸绶ㄧ▼鎬�
- 鍥炶畝鍔熻兘
?100%宸ュ粻娓│
?0.15渭m8灞ら噾灞伐钘濓紝0.12渭m楂橀�熸櫠楂旂
?1.5V(VCCINT)鏍稿績闆绘簮锛屽皥鐢�3.3V VCCAUX杓斿姪鍜孷CCO I / O闆绘簮
?IEEE 1149.1鍏煎閭婄晫鎺冩弿閭忚集鏀寔
?閲囩敤鐒￠墰灏佽鐨勭窔鐒夿GA鍣ㄤ欢
?涓夌ó妯�(bi膩o)婧�(zh菙n)绮剧窗闁撹窛(0.80 mm锛�1.00 mm鍜�1.27 mm)鐨勫�掕鑺墖鍜屽紩绶氶嵉鍚堢悆鏌甸櫍鍒�(BGA)灏佽
XC2V4000-4FF1152I绗﹁櫉
XC2V4000-4FF1152I鑵冲嵃
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