XC2V2000-4FGG676C 鏅�(sh铆)闁擄細2023/7/12 11:30:24 闁辫畝锛�1050

鎻忚堪

銆€銆€XC2V2000-4FGG676C鏄偤楂樻€ц兘寰炰綆瀵嗗害鍒伴珮瀵嗗害瑷�(sh猫)瑷�(j矛)鑰岄枊鐧�(f膩)鐨勫钩鑷�(t谩i)FPGA锛屽熀浜巐Pcores鍜屽畾鍒舵ā濉�銆傝┎绯诲垪鐐洪浕淇�銆佺劇绶�銆佺恫(w菐ng)绲�(lu貌)銆佽闋诲拰DSP鎳�(y墨ng)鐢ㄦ彁渚涘畬鏁寸殑瑙ｆ焙鏂规锛屽寘鎷琍CI銆丩VDS鍜孌DR鎺ュ彛銆傚厛閫�(j矛n)鐨�0.15um/0.12umCMOS8灞ら噾灞伐钘濆拰Virtex-ll鏋舵(g貌u)閲濆皪(du矛)楂橀€熷拰浣庡姛鑰楅€�(j矛n)琛屼簡鍎�(y艒u)鍖�銆傜祼(ji茅)鍚堜簡寤ｆ硾鐨勯潏娲荤壒鎬у拰楂橀仈(d谩)1000钀€�(g猫)绯荤当(t菕ng)闁€鐨勫ぇ鑼冨湇瀵嗗害锛屽寮�(qi谩ng)浜嗗彲绶ㄧ▼閭忚集瑷�(sh猫)瑷�(j矛)鑳藉姏锛屾槸鎺╄啘绶ㄧ▼闁€闄ｅ垪鐨勫挤(qi谩ng)澶ф浛浠ｅ搧銆�

鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸瀷铏�(h脿o)	XC2V2000-4FGG676C
鎻忚堪	闆嗘垚闆昏矾FPGA 456 I / O 676FBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鍒堕€犲晢	Xilinx鍏徃
绯诲垪	Virtex?-II
鎵撳寘	鎵樼洡
闆诲-闆绘簮	1.425V?1.575V
宸ヤ綔婧害	0掳C?85掳C(TJ)
鍖呰/绠�	676-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	676-FBGA(27x27)
鍩烘湰闆朵欢铏�(h脿o)	XC2V2000

鐢�(ch菐n)鍝佸湒鐗�

XC2V2000-4FGG676C

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绺絉AM浣�	1032192
鏈€澶ф檪(sh铆)閻橀牷鐜�	650.0鍏嗚但
CLB-Max鐨勭祫鍚堝欢閬�	0.44绱嶇
JESD-30浠ｇ⒓	S-PBGA-B676
JESD-609浠ｇ⒓	e1
CLB鏁�(sh霉)閲�	2688.0
绛夋晥闁€鏁�(sh霉)	2000000.0
杓稿叆鏁�(sh霉)閲�	456.0
閭忚集鍠厓鏁�(sh霉)	24192.0
杓稿嚭鏁�(sh霉)閲�	456.0
绔瓙鏁�(sh霉)	676
鏈€浣庡伐浣滄韩搴�	0鈩�
鏈€楂樺伐浣滄韩搴�	85鈩�
绲勭箶	2688 CLBS锛�2000000鍊�(g猫)闁€
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA676,26X26,40
鍖呰褰㈢媭	鍥涙柟褰�
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
宄板€煎洖娴佹韩搴�(鈩�)	250
闆绘簮	1.5,1.5 / 3.3,3.3
搴ч珮	2.6姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	1.5浼�
鏈€灏忎緵闆婚浕澹�	1.425浼�
鏈€澶ч浕婧愰浕澹�	1.575浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆(j铆)	鍏朵粬
绲傜瀹屾垚	閷�/閵€/閵�(Sn95.5Ag4.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅�(sh铆)闁揁宄板€煎洖娴佹韩搴�-鏈€澶у€�(绉�)	30
闀峰害	27.0姣背
瀵害	27.0姣背
鍒堕€犲晢鍖呰瑾槑	27 X 27 MM锛�1 MM闁撹窛锛岀劇閴�锛孧S-034AAL-1锛孎(xi脿n)BGA-676

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

姘村垎鏁忔劅鎬ф按骞�(MSL)	3(168灏忔檪(sh铆))
绗﹀悎姝愮洘RoHS	鏄�

CAD妯″瀷

XC2V2000-4FGG676C绗﹁櫉(h脿o)

XC2V2000-4FGG676C鑵冲嵃

灏佽

XC2V2000-4FGG676C灏佽

鏇夸唬鍨嬭櫉(h脿o)

鍨嬭櫉(h脿o)	鍒堕€犲晢	鍝佸悕	鎻忚堪
XC2V2000-6FGG676C	璩介潏鎬�	FPGA鑺墖	24192Cells 820MHz 0.15um 1.5V 676Pin FBGA
XC2V2000-4FGG676I	璩介潏鎬�	FPGA鑺墖	24192Cells 650MHz 0.15um 1.5V 676Pin FBGA
XC2V2000-5FGG676C	璩介潏鎬�	FPGA鑺墖	24192Cells 750MHz 0.15um 1.5V 676Pin FBGA