鏅傞枔锛�2023/8/2 18:04:10
闁辫畝锛�589
鐢�(ch菐n)鍝佸瀷铏� | XC2V2000-4FG676I |
鎻忚堪 | 闆嗘垚闆昏矾FPGA 456 I/O 676FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | Xilinx鍏徃 |
绯诲垪 | Virtex?-II |
闆朵欢鐙�鎱�(t脿i) | 閬庢檪鐨� |
闆诲-闆绘簮 | 1.425V?1.575V |
宸ヤ綔婧害 | -40掳C?100掳C(TJ) |
鍖呰/绠� | 676-BBGA锛孎(xi脿n)CBGA |
渚涙噳鍟嗚ō鍌欏寘瑁� | 676-FCBGA(27x27) |
鍩烘湰闆朵欢铏� | XC2V2000 |
XC2V2000-4FG676I
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
鐙�鎱�(t脿i) | 宸插仠鐢�(ch菐n) |
鏈�澶ф檪閻橀牷鐜� | 650.0鍏嗚但 |
CLB-Max鐨勭祫鍚堝欢閬� | 0.44绱嶇 |
JESD-30浠ｇ⒓ | S-PBGA-B676 |
JESD-609浠ｇ⒓ | 00 |
绺絉AM浣� | 1032192 |
CLB鏁�(sh霉)閲� | 2688.0 |
绛夋晥闁�鏁�(sh霉) | 2000000.0 |
杓稿叆鏁�(sh霉)閲� | 456.0 |
閭忚集鍠厓鏁�(sh霉) | 24192.0 |
杓稿嚭鏁�(sh霉)閲� | 456.0 |
绔瓙鏁�(sh霉) | 676 |
绲勭箶 | 2688 CLBS锛�2000000鍊嬮杸 |
宄板�煎洖娴佹韩搴�(鈩�) | 225 |
闆绘簮 | 1.5,1.5 / 3.3,3.3 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
搴ч珮 | 2.6姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲妯欑ū | 1.5浼� |
鏈�灏忎緵闆婚浕澹� | 1.425浼� |
鏈�澶ч浕婧愰浕澹� | 1.575浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛� | CMOS |
绲傜瀹屾垚 | 閷�/閴�(Sn63Pb37) |
绲傜琛ㄦ牸 | 鐞� |
绔瓙闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴︽渶澶у��(绉�) | 30 |
闀峰害 | 27.0姣背 |
瀵害 | 27.0姣背 |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呰绛夋晥浠ｇ⒓ | BGA676,26X26,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰褰㈠紡 | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 27 X 27 MM锛�1 MM闁撹窛锛孧S-034AAL-1锛孎(xi脿n)BGA-676 |
鐒￠墰鐙�鎱�(t脿i)/RoHS鐙�鎱�(t脿i) | 鍖呭惈閴�/ RoHS涓嶅悎瑕�(gu墨) |
姘村垎鏁忔劅鎬ф按骞�(MSL) | 3(168灏忔檪) |
XC2V2000-4FG676I绗﹁櫉
XC2V2000-4FG676I鑵冲嵃
