鍨嬭櫉锛歑C2S30-5TQ144C
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歋partan-II
銆�銆�灏佽�濋�炲瀷锛歍QFP-144
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細30,000
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏�(n猫i)缃�
銆�銆�RAM 璩囨簮锛�76,800 bits
銆�銆�DSP Slice 鏁�(sh霉)閲忥細鐒�
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細114
銆�銆�宸ヤ綔闆诲�擄��1.8V 鏍搁浕澹� / 3.3V I/O 闆诲��
銆�銆�鏈�灏忓伐浣滄韩搴︼細-40掳C
銆�銆�鏈�澶у伐浣滄韩搴︼細+85掳C
銆�銆�鏅傞悩闋荤巼鑼冨湇锛氶珮閬� 200 MHz
銆�銆�閰嶇疆鏂瑰紡锛氬緸澶栭儴 PROM 鎴� JTAG

XC2S30-5TQ144C 鐨勪富瑕佺壒鎬у寘鎷�锛�
銆�銆�1. 楂樺害鍙�绶ㄧ▼鎬э紝鏀�鎸佺敤鎴舵牴鎿�(j霉)鍏烽珨闇�姹傝嚜瀹氱京鏁�(sh霉)瀛楅倧杓�鍔熻��銆�
銆�銆�2. 鍏�(n猫i)缃� Block RAM 妯″��锛屽彲浠ュ�︾��(xi脿n)鏁�(sh霉)鎿�(j霉)绶╂矕銆佹煡鎵捐〃绛夊姛鑳�銆�
銆�銆�3. 鎻愪緵澶氶仈 114 鍊嬮�氱敤杓稿叆杓稿嚭锛圛/O锛夊紩鑵筹紝鏀�鎸佸�氱ó闆诲钩妯欐簴銆�
銆�銆�4. 鏀�鎸佸�氱ó閰嶇疆妯″紡锛屼緥濡傚緸涓茶�� PROM 鍟熷嫊鎴栭�氶亷 JTAG 閫茶�岃��(di脿o)瑭�銆�
銆�銆�5. 鍏�(n猫i)閮ㄨ硣婧愯睈瀵�锛屽寘鍚� CLB锛圕onfigurable Logic Blocks锛�銆両OBs锛圛nput/Output Blocks锛変互鍙婂皥鐢ㄦ檪閻樼�＄悊鍠�鍏冦��
銆�銆�6. 杓冧綆鐨勯潨鎱�(t脿i)鍔熻��锛岄潪甯搁仼鍚堝皪鍔熻�楁晱鎰熺殑鎳�(y墨ng)鐢ㄥ牬鏅�銆�
銆�銆�7. 鎻愪緵鍏ㄩ潰鐨勮ō(sh猫)瑷堝伐鍏锋敮鎸�锛屽寘鎷� Xilinx ISE Design Suite锛屾柟渚块枊鐧�(f膩)鑰呴�茶�屽揩閫熷師鍨嬮枊鐧�(f膩)鑸囬�楄��銆�

XC2S30-5TQ144C 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 宸ユキ(y猫)鑷�鍕曞寲鎺у埗涓�鐨勪俊铏熻檿鐞嗚垏鍗�(xi茅)璀拌綁(zhu菐n)鎻�銆�
銆�銆�2. 閫氫俊绯荤当(t菕ng)涓�鐨勫熀甯惰檿鐞嗗拰鏁�(sh霉)鎿�(j霉)鍖呰В鏋�銆�
銆�銆�3. 瑕栭牷鑸囧湒鍍忚檿鐞�锛屽�傚垎杈ㄧ巼杞�(zhu菐n)鎻涘拰鑹插僵鏍℃��銆�
銆�銆�4. 閱�(y墨)鐧傝ō(sh猫)鍌欎腑鐨勫�︽檪鏁�(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞嗐��
銆�銆�5. 娑堣不椤為浕瀛愮敘(ch菐n)鍝佷腑鐨勫祵鍏ュ紡鎺у埗鍣�銆�
銆�銆�6. 娓�瑭︽脯閲忓剙鍣ㄤ腑鐨勯珮閫熸暩(sh霉)鎿�(j霉)閲囬泦鑸囧垎鏋�銆�
銆�銆�7. 鏁欒偛鍜岀�戠爺闋�(l菒ng)鍩熺殑 FPGA 瀵﹂�楀钩鑷�銆�

XC2S30-6TQ144C
銆�銆�XC2S50-5TQ144C
銆�銆�XC2S50-6TQ144C