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XC2S30-5CS144C 鏄� Xilinx 鍏徃 Spartan-II 绯诲垪鐨� FPGA锛堢従鍫村彲绶ㄧ▼闁�闄ｅ垪锛夎姱鐗囥�傝┎绯诲垪灏堢偤浣庢垚鏈�銆佷綆鍔熻�楁噳鐢ㄨō瑷�锛岄仼鐢ㄤ簬娑堣不闆诲瓙銆侀�氫俊銆佸伐妤�(y猫)鎺у埗绛夐牁鍩�銆俋C2S30 鍖呭惈澶х磩 3 钀�嬬郴绲�(t菕ng)闁�鍜� 384 鍊嬮倧杓柈鍏冿紝鑳藉婊胯冻涓皬鍨嬭ō瑷堥渶姹�銆�
銆�銆�瑭插瀷铏熶腑鐨勫叿楂斿惈缇╁涓嬶細XC 琛ㄧず Xilinx 鑺墖锛�2S 琛ㄧず Spartan-II 绯诲垪锛�30 琛ㄧず绱� 3 钀郴绲�(t菕ng)闁�瑕�(gu墨)妯★紝5 琛ㄧず閫熷害绛夌礆锛�-5锛�锛孋S144 琛ㄧず灏佽椤炲瀷鐐� 144 寮曡叧 CSBGA 灏佽锛孋 琛ㄧず鍟嗙敤绱氭韩搴﹁寖鍦嶏紙0掳C 鑷� +70掳C锛�銆�
鍨嬭櫉锛歑C2S30-5CS144C
銆�銆�绯诲垪锛歋partan-II
銆�銆�寤犲晢锛歑ilinx
銆�銆�閭忚集鍠厓鏁革細384
銆�銆�绯荤当(t菕ng)闁�鏁革細30K
銆�銆�RAM锛�16KB
銆�銆�涔樻硶鍣細4
銆�銆�閰嶇疆妯″紡锛欱oundary Scan 鍜� JTAG
銆�銆�渚涢浕闆诲锛�2.5V 鏍稿績闆诲锛�3.3V I/O 闆诲
銆�銆�宸ヤ綔婧害锛�0掳C 鑷� +70掳C (鍟嗙敤绱�)
銆�銆�灏佽锛�144 寮曡叧 CSBGA
XC2S30-5CS144C 鎻愪緵浜嗗绋棞閸电壒鎬э細
銆�銆�1. 楂樻�ц兘鑸囦綆鍔熻�楋細閫氶亷鍎�(y艒u)鍖栫殑鏋舵锛屾 FPGA 鍦ㄥ鐝鹃珮鎬ц兘鐨勫悓鏅備繚鎸佽純浣庣殑鍔熻��锛岄潪甯搁仼鍚堥浕姹犱緵闆昏ō鍌�銆�
銆�銆�2. 鍏х疆纭牳妯″锛氬寘鎷� 16KB 鐨勫祵鍏ュ紡濉� RAM 鍜� 4 鍊� 18x18 浣嶄箻娉曞櫒锛屾湁鍔╀簬鍔犻�熸暩瀛椾俊铏熻檿鐞嗗拰鏁告摎瀛樺劜浠诲嫏銆�
銆�銆�3. 鍙摯灞曟�э細鏀寔澶氱ó閰嶇疆妯″紡锛屽閭婄晫鎺冩弿鍜� JTAG 鎺ュ彛锛屼究浜庤垏鍏朵粬绯荤当(t菕ng)绲勪欢闆嗘垚銆�
銆�銆�4. 杓稿叆/杓稿嚭璩囨簮璞愬瘜锛氬叿鍌欏绲勫彲绶ㄧ▼ I/O 寮曡叧锛岄仼鎳夊悇绋帴鍙ｉ渶姹�銆�
銆�銆�5. 鍟嗙敤绱氭韩搴﹁寖鍦嶏細閬╁悎鍦ㄦ婧栧鍏х挵(hu谩n)澧冩浠朵笅閬嬭鐨勬噳鐢ㄥ牬鏅��
銆�銆�6. 鏄撲簬浣跨敤鐨勮ō瑷堝伐鍏凤細Xilinx 鎻愪緵 ISE Design Suite 宸ュ叿閺�锛岀啊鍖栭枊鐧�(f膩)娴佺▼骞剁府鐭笂甯傛檪闁�銆�
XC2S30-5CS144C 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 娑堣不椤為浕瀛愮敘鍝侊細渚嬪鏁哥⒓鐩告銆佹父鎴叉鍜岃闋昏檿鐞嗚ō鍌�銆�
銆�銆�2. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬鎺у埗闈㈡澘銆丳LC 鍜屽鏅傛暩鎿氶噰闆嗙郴绲�(t菕ng)銆�
銆�銆�3. 閫氫俊瑷倷锛氶仼鐢ㄤ簬灏忓瀷璺敱鍣ㄣ�佷氦鎻涙浠ュ強鐒＄窔鎺ュ叆榛�銆�
銆�銆�4. 宓屽叆寮忕郴绲�(t菕ng)锛氬彲鐢ㄤ簬閱�(y墨)鐧傚剙鍣ㄣ�佹脯瑭︽脯閲忚缃拰姹借粖闆诲瓙涓�銆�
銆�銆�5. 鏁欒偛鑸囩鐮旓細鐢变簬鍏剁稉婵熷鎯犱笖鍔熻兘寮峰ぇ锛屾槸瀛哥繏 FPGA 绶ㄧ▼鐨勭悊鎯冲钩鑷�銆�
XC2S30-6CS144C
銆�銆�XC2S30-5TQ144C
