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鍣ㄤ欢椤炲瀷锛欶PGA
銆€銆€绯诲垪锛歋partan-II
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細15,000 CLBs (绱勭浉鐣�(d膩ng)浜� 150K ASIC gates)
銆€銆€閰嶇疆瀛樺劜鍣細832 KB
銆€銆€鐢ㄦ埗 I/O 鏁�(sh霉)閲忥細312
銆€銆€DSP Slice锛氱劇
銆€銆€鏈€澶у伐浣滈牷鐜囷細239 MHz
銆€銆€闆绘簮闆诲锛�1.8V 鏍稿績锛�3.3V I/O
銆€銆€灏佽褰㈠紡锛欶GG456
銆€銆€閫熷害绛夌礆锛�-6

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