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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > ST7FLIT15BY1M6

ST7FLIT15BY1M6 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2025/5/13 13:47:05 鏌ョ湅 闁辫畝锛�18

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鍙冩暩(sh霉)

宸ヤ綔闆诲锛�2.0V鑷�3.6V
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C鑷�+85掳C
銆�銆�瀛樺劜鍣細16KB Flash锛�1KB RAM
銆�銆�鏅傞悩闋荤巼锛氭渶楂�24MHz
銆�銆�I/O绔彛鏁�(sh霉)閲忥細29
銆�銆�灏佽褰㈠紡锛歀QFP48

鐗规��

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鏇夸唬鍨嬭櫉

ST7FLIT16C8T6, ST7FLIT15B8T6

st7flit15by1m6鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

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  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

st7flit15by1m6璩囨枡 鏇村>

  • 鍨嬭櫉
  • 鎻忚堪
  • 鍝佺墝
  • 闁辫涓嬭級

st7flit15by1m6鍙冩暩(sh霉)

  • 鍏跺畠鏈夐棞(gu膩n)鏂囦欢ST7LIT15BY1 View All Specifications
  • 妯�(bi膩o)婧�(zh菙n)鍖呰49
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - 寰帶鍒跺櫒锛�
  • 绯诲垪ST7
  • 鏍稿績铏曠悊鍣�ST7
  • 鑺珨灏哄8-浣�
  • 閫熷害8MHz
  • 閫ｉ�氭��SPI
  • 澶栧湇瑷�(sh猫)鍌�LVD锛孭OR锛孭WM锛學DT
  • 杓稿叆/杓稿嚭鏁�(sh霉)11
  • 绋嬪簭瀛樺劜鍣ㄥ閲�4KB锛�4K x 8锛�
  • 绋嬪簭瀛樺劜鍣ㄩ鍨�闁冨瓨
  • EEPROM 澶у皬-
  • RAM 瀹归噺256 x 8
  • 闆诲 - 闆绘簮 (Vcc/Vdd)2.7 V ~ 5.5 V
  • 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒A/D 5x10b
  • 鎸暕鍣ㄥ瀷鍏�(n猫i)閮�
  • 宸ヤ綔婧害-40°C ~ 85°C
  • 灏佽/澶栨16-SOIC锛�0.295"锛�7.50mm 瀵級
  • 鍖呰绠′欢
  • 閰嶇敤497-5049-ND - KIT STARTER RAISONANCE ST7FLITE497-5046-ND - KIT TOOL FOR ST7/UPSD/STR7 MCU
  • 鍏跺畠鍚嶇ū497-8245-5ST7FLIT15BY1M6-ND