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MIMX8UX5AVLFZAC 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2024/5/7 15:36:52 鏌ョ湅 闁辫畝锛�170

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銆�銆�寤犲晢鍨嬭櫉(h脿o)锛歁IMX8UX5AVLFZAC

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銆�銆�鍨嬭櫉(h脿o)浠嬬垂锛�鏄敱i.MX8QuadXPlus鍜�8DualXPlus绲勬垚鐨刬.MX8X瀹舵棌

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銆�銆�寤ｆ硾鐨勫鍦�I/o锛屽CAN锛屽苟琛屾垨MIPICSI鐩告(j墨)杓稿叆锛屽崈鍏嗕互澶恫(w菐ng)锛孶SB2.0OTG,USB3.0(8QuadXPlus/8DualXPlus鍍�)锛孉DC鍜孭CIe3.0鎻愪緵鑳芥彁渚涗护浜哄嵃璞℃繁鍒荤殑闈堟椿鎬с��

涓枃鍙冩暩(sh霉)

瀹夎棰�(f膿ng)鏍�:SMD/SMT鏈�澶у伐浣滄韩搴�:+ 125 C
灏佽 / 绠遍珨:FCPBGA-1296灏佽:Tray
绯诲垪:i.MX 8DualX鍟嗘(bi膩o):NXP Semiconductors
鏍稿績:ARM Cortex A35, ARM Cortex M4F鏁�(sh霉)鎿�(j霉) RAM 澶у皬:512 kB
鍏�(n猫i)鏍告暩(sh霉)閲�:5 CoreI/O 闆诲:1.8 V, 3.3 V
鏁�(sh霉)鎿�(j霉)绺界窔瀵害:64 bit鎺ュ彛椤炲瀷:CAN, I2C, SPI, USART, USB
鏈�澶ф檪(sh铆)閻橀牷鐜�:264 MHz, 1.2 GHz瀛樺劜(ch菙)椤炲瀷:DDR3L, LPDDR4, SRAM
L1绶╁瓨鎸囦护瀛樺劜(ch菙)鍣�:16 kB, 4 x 32 kB婵曞害鏁忔劅鎬�:Yes
L1绶╁瓨鏁�(sh霉)鎿�(j霉)瀛樺劜(ch菙)鍣�:16 kB, 4 x 32 kB杓稿叆/杓稿嚭绔暩(sh霉)閲�:609 I/O
宸ヤ綔闆绘簮闆诲:1 V瑷�(j矛)鏅�(sh铆)鍣�/瑷�(j矛)鏁�(sh霉)鍣ㄦ暩(sh霉)閲�:1 x 32 bit
鏈�灏忓伐浣滄韩搴�:- 40 C鐪嬮杸鐙楄▓(j矛)鏅�(sh铆)鍣�:Watchdog Timer

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