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鍏�(n猫i)鏍革細ARM Cortex-M0+
銆€銆€涓婚牷锛氭渶楂� 48 MHz
銆€銆€闁冨瓨锛�512 KB
銆€銆€SRAM锛�64 KB
銆€銆€灏佽锛歀QFP-144
銆€銆€宸ヤ綔闆诲锛�3.3V
銆€銆€宸ヤ綔婧害锛�-40掳C 鑷� +125掳C
銆€銆€I/O寮曡叧锛氬閬�(d谩) 118 鍊�
銆€銆€ADC閫氶亾锛氭渶澶� 16 鍊�
銆€銆€瀹氭檪鍣細鏀寔澶氬€嬪畾鏅傚櫒妯″
銆€銆€閫氫俊鎺ュ彛锛氬寘鎷� SPI銆両2C銆乁ART銆丆AN-FD

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