EP4SGX530KH40I3N 鏅�(sh铆)闁擄細2023/8/1 11:15:38 闁辫畝锛�285

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鐢�(ch菐n)鍝佸瀷铏�	EP4SGX530KH40I3N
鎻忚堪	闆嗘垚闆昏矾FPGA 744 I/O 1517HBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鍒堕€犲晢	鑻辩壒鐖�
绯诲垪	Stratix?IV GX
鎵撳寘	鎵樼洡
闆朵欢鐙€鎱�(t脿i)	娲绘€�
闆诲-闆绘簮	0.87V?0.93V
宸ヤ綔婧害	-40掳C?100掳C(TJ)
鍖呰/绠�	1517-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	1517-HBGA(42.5x42.5)
鍩烘湰闆朵欢铏�	EP4SGX530

鐢�(ch菐n)鍝佸湒鐗�

EP4SGX530KH40I3N

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎姝愮洘RoHS	鏄�
鐙€鎱�(t脿i)	杞�(zhu菐n)绉�
鏈€澶ф檪(sh铆)閻橀牷鐜�	717.0鍏嗚但
JESD-30浠ｇ⒓	S-PBGA-B1517
JESD-609浠ｇ⒓	1铏�
绺絉AM浣�	28033024
CLB鏁�(sh霉)閲�	212480.0
杓稿叆鏁�(sh霉)閲�	744.0
閭忚集鍠厓鏁�(sh霉)	531200.0
杓稿嚭鏁�(sh霉)閲�	744.0
绔瓙鏁�(sh霉)	1517
绲勭箶	212480 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	245
闆绘簮	0.9,1.2 / 3,1.5,2.5
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
搴ч珮	3.8姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	0.9浼�
鏈€灏忎緵闆婚浕澹�	0.87浼�
鏈€澶ч浕婧愰浕澹�	0.93浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
绲傜瀹屾垚	閷�/閵€/閵�(Sn / Ag / Cu)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅�(sh铆)闁揁宄板€煎洖娴佹韩搴︽渶澶у€�(绉�)	40
闀峰害	42.5姣背
瀵害	42.5姣背
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA1517,39X39,40
鍖呰褰㈢媭	寤ｅ牬
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	鐒￠墰锛孒BGA-1517

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

鐒￠墰鐙€鎱�(t脿i)/RoHS鐙€鎱�(t脿i)	鐒￠墰/绗﹀悎RoHS
姘村垎鏁忔劅鎬ф按骞�(MSL)	3(168灏忔檪(sh铆))

鐗归粸(di菐n)

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鍏锋湁宓屽叆寮廝CIe纭琁P妯″鐨勫畬鏁碢CIe鍗�(xi茅)璀拌В姹烘柟妗�锛岄€欎簺妯″瀵�(sh铆)鐝�(xi脿n)PHY-MAC灞�锛屾暩(sh霉)鎿�(j霉)閺堣矾灞ゅ拰浜嬪嫏(w霉)铏曠悊灞ゅ姛鑳�
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姣忓€�(g猫)閫氶亾鐨勫吀鍨嬬墿鐞嗕粙璩�(zh矛)闄勪欢(PMA)鍔熻€楀垎鍒ョ偤3.125 Gbps鍜�100 mW锛�6.375 Gbps鏅�(sh铆)鐐�135 mW
姣忚嚭瑷�(sh猫)鍌�72,600鑷�813,050绛夋晥LE
7,370鑷�33,294 Kb鐨勫寮�(qi谩ng)鍨婽riMatrix瀛樺劜鍣�锛岀敱涓夌óRAM濉婂ぇ灏忕祫鎴�锛屽彲瀵�(sh铆)鐝�(xi脿n)鐪熸鐨勯洐绔彛瀛樺劜鍣ㄥ拰FIFO绶╂矕鍗€(q奴)
楂橀€熸暩(sh霉)瀛椾俊铏熻檿鐞�(DSP)妯″锛屾渶楂樺彲閰嶇疆鐐�9 x 9浣�锛�12 x 12浣�锛�18 x 18浣嶅拰36 x 36浣嶅叏绮惧害涔樻硶鍣紝鏈€楂橀牷鐜囩偤600 MHz
姣忓€�(g猫)瑷�(sh猫)鍌欐渶澶�16鍊�(g猫)鍏ㄥ眬鏅�(sh铆)閻�(GCLK)锛�88鍊�(g猫)鍗€(q奴)鍩熸檪(sh铆)閻�(RCLK)鍜�132鍊�(g猫)澶栧湇鏅�(sh铆)閻�(PCLK)
鍙法绋嬮浕婧愭妧琛�(sh霉)锛屽彲鍦ㄦ渶澶х▼搴﹂檷浣庡姛鑰楃殑鍚屾檪(sh铆)鏈€澶у寲瑷�(sh猫)鍌欐€ц兘
澶氶仈(d谩)1,120鍊�(g猫)鐢ㄦ埗I / O寮曡叧甯冪疆鍦�24鍊�(g猫)妯″鍖朓 / O bank涓�锛岄€欎簺妯″鏀寔寤ｆ硾鐨勫柈绔拰宸垎I / O妯�(bi膩o)婧�(zh菙n)
鏀寔澶氶仈(d谩)24鍊�(g猫)妯″鍖朓 / O bank涓婄殑楂橀€熷閮ㄥ瓨鍎插櫒鎺ュ彛锛屽寘鎷珼DR锛孌DR2锛孌DR3 SDRAM锛孯LDRAM II锛孮DR II鍜孮DR II + SRAM
鍏锋湁涓茶鍣�/瑙ｄ覆鍣�(SERDES)锛屽嫊(d貌ng)鎱�(t脿i)鐩镐綅灏嶆簴(zh菙n)(DPA)鍜宻oft-CDR闆昏矾鐨勯珮閫烲VDS I / O鏀寔锛屾暩(sh霉)鎿�(j霉)閫熺巼楂橀仈(d谩)1.6 Gbps
鏀寔婧愬悓姝ョ附绶氭(bi膩o)婧�(zh菙n)锛屽寘鎷琒GMII锛孏bE锛孲PI-4闅庢2(POS-PHY绱氬垾4)锛孲FI-4.1锛孹SBI锛孶TOPIA IV锛孨PSI鍜孋SIX-L1
Stratix IV E鍣ㄤ欢鐨勫紩鑵�锛屽叾瑷�(sh猫)瑷�(j矛)鍏佽ū浠ユ渶灏忕殑PCB褰遍熆寰濻tratix III閬风Щ鍒癝tratix IV E Stratix IV GX鍣ㄤ欢姣忓€�(g猫)鍣ㄤ欢鎻愪緵澶氶仈(d谩)48鍊�(g猫)鍩轰簬鍏ㄩ洐宸DR鐨勬敹鐧�(f膩)鍣ㄩ€氶亾锛�
48鍊�(g猫)鏀剁櫦(f膩)鍣ㄩ€氶亾涓殑32鍊�(g猫)鍏锋湁灏堢敤鐨勭墿鐞嗙法纰煎瓙灞�(PCS)鍜岀墿鐞嗕粙璩�(zh矛)闄勪欢(PMA)闆昏矾锛屽苟鏀寔600 Mbps鑷�8.5 Gbps涔嬮枔鐨勬暩(sh霉)鎿�(j霉)閫熺巼
鍏朵綑16鍊�(g猫)鏀剁櫦(f膩)鍣ㄩ€氶亾鍏锋湁灏堢敤浜嶱MA鐨勫皥鐢ㄩ浕璺紝骞舵敮鎸�600 Mbps鑷�6.5 Gbps涔嬮枔鐨勬暩(sh霉)鎿�(j霉)閫熺巼
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