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鐢�(ch菐n)鍝佸瀷铏�	EP4SGX530KF43C2N
鎻忚堪	闆嗘垚闆昏矾FPGA 880 I/O 1760FBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鍒堕€犲晢	鑻辩壒鐖�
绯诲垪	Stratix?IV GX
鎵撳寘	鎵樼洡
闆朵欢鐙€鎱�(t脿i)	娲绘€�
闆诲-闆绘簮	0.87V?0.93V
宸ヤ綔婧害	0掳C?85掳C(TJ)
鍖呰/绠�	1760-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	1760-FBGA锛孎(xi脿n)C(42.5x42.5)
鍩烘湰闆朵欢铏�	EP4SGX530

鐢�(ch菐n)鍝佸湒鐗�

EP4SGX530KF43C2N

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎姝愮洘RoHS	鏄�
鐙€鎱�(t脿i)	杞�(zhu菐n)鍏�
鏈€澶ф檪閻橀牷鐜�	800.0鍏嗚但
JESD-30浠ｇ⒓	S-PBGA-B1760
JESD-609浠ｇ⒓	1铏�
绺絉AM浣�	28033024
CLB鏁�(sh霉)閲�	212480.0
杓稿叆鏁�(sh霉)閲�	880.0
閭忚集鍠厓鏁�(sh霉)	531200.0
杓稿嚭鏁�(sh霉)閲�	880.0
绔瓙鏁�(sh霉)	1760
鏈€浣庡伐浣滄韩搴�	0鈩�
鏈€楂樺伐浣滄韩搴�	85鈩�
绲勭箶	212480 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	245
闆绘簮	0.9,1.2 / 3,1.5,2.5
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
搴ч珮	3.7姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲妯欑ū	0.9浼�
鏈€灏忎緵闆婚浕澹�	0.87浼�
鏈€澶ч浕婧愰浕澹�	0.93浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆	鍏朵粬
绲傜瀹屾垚	閷�/閵€/閵�(Sn / Ag / Cu)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅傞枔@宄板€煎洖娴佹韩搴︽渶澶у€�(绉�)	40
闀峰害	42.5姣背
瀵害	42.5姣背
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA1760,42X42,40
鍖呰褰㈢媭	寤ｅ牬
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	鐒￠墰锛孎(xi脿n)BGA-1760

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

鐒￠墰鐙€鎱�(t脿i)/RoHS鐙€鎱�(t脿i)	鐒￠墰/绗﹀悎RoHS
姘村垎鏁忔劅鎬ф按骞�(MSL)	3(168灏忔檪)

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灏堢敤闆昏矾鍙敮鎸佹祦琛岀殑涓茶鍗�(xi茅)璀扮殑鐗╃悊灞ゅ姛鑳斤紝渚嬪PCI Express(PCIe)(PIPE)Gen1鍜孏en2锛孏bps浠ュお缍�(w菐ng)(GbE)锛屼覆琛孯apidIO锛孲ONET / SDH锛孹AUI / HiGig锛�(OIF)CEI-6G 锛孲D / HD / 3G-SDI锛屽厜绾栭€氶亾锛孲FI-5鍜孖nterlaken
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鍏稿瀷鐨勭墿鐞嗕粙璩�(zh矛)闄勪欢(PMA)鍔熻€楃偤姣忛€氶亾3.125 Gbps鏅�100 mW鍜�6.375 Gbps鏅�135 mW
72600鍒版瘡鍊嬭ō(sh猫)鍌�813050绱氱暥閲忕殑LE
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楂橀仈600 MHz鐨勯珮閫熸暩(sh霉)瀛椾俊铏熻檿鐞�(DSP)妯″鍙厤缃偤9 x 9浣�锛�12 x 12浣�锛�18 x 18浣嶅拰36 x 36浣嶅叏绮惧害涔樻硶鍣�
姣忓€嬭ō(sh猫)鍌欐渶澶�16鍊嬪叏灞€鏅傞悩(GCLK)锛�88鍊嬪崁(q奴)鍩熸檪閻�(RCLK)鍜�132鍊嬪鍦嶆檪閻�(PCLK)
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鏀寔澶氶仈24鍊嬫ā濉婂寲I / O bank涓婄殑楂橀€熷閮ㄥ瓨鍎插櫒鎺ュ彛锛屽寘鎷珼DR锛孌DR2锛孌DR3 SDRAM锛孯LDRAM II锛孮DR II鍜孮DR II + SRAM
鍏锋湁涓茶鍣�/瑙ｄ覆鍣�(SERDES)锛屽嫊鎱�(t脿i)鐩镐綅灏嶆簴(DPA)鍜宻oft-CDR闆昏矾鐨勯珮閫烲VDS I / O鏀寔锛屾暩(sh霉)鎿�(j霉)閫熺巼楂橀仈1.6 Gbps
鏀寔婧愬悓姝ョ附绶氭婧�锛屽寘鎷琒GMII锛孏bE锛孲PI-4 2鏈�(POS-PHY 4绱�)锛孲FI-4.1锛孹SBI锛孶TOPIA IV锛孨PSI鍜孋SIX-L1
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