鍨嬭櫉(h脿o)锛欵P4SGX530HH35C4N
銆�銆�FPGA 绯诲垪锛歋tratix GX
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細绱� 53 钀�(w脿n)
銆�銆�RAM 绺�?c猫)钀樻禋鏉璼 9.6Mb
銆�銆�DSP 妯″�婃��(sh霉)閲忥細288
銆�銆�閰嶇疆闁冨瓨锛氫笉闆嗘垚
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細769
銆�銆�灏佽�濋�炲瀷锛欶BGA-1196
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏細宸ユ��(y猫)绱�(j铆)锛�-40掳C 鑷� +85掳C锛�
銆�銆�宸ヨ棟鍒剁▼锛�90nm
銆�銆�鏍稿績闆诲�擄��1.2V
銆�銆�I/O 闆诲�擄��1.8V/2.5V/3.3V

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銆�銆�1. 楂樻�ц兘鏋舵��(g貌u)锛氬熀浜� Altera 鐨� Stratix GX 绯诲垪瑷�(sh猫)瑷�(j矛)锛屽叿鏈夊劒(y艒u)鍖栫殑鏅�(sh铆)搴忛枆鍚堝拰鍕�(d貌ng)鎱�(t脿i)鍔熻�楃�＄悊銆�
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銆�銆�3. 澶ц��(gu墨)妯￠倧杓�闄ｅ垪锛氭搧鏈夎秴閬�(gu貌) 53 钀�(w脿n)鍊�(g猫)閭忚集鍠�鍏�锛岄仼鍚堝��(sh铆)鐝�(xi脿n)寰�(f霉)闆滅畻娉曞拰绯荤当(t菕ng)绱�(j铆)瑷�(sh猫)瑷�(j矛)銆�
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銆�銆�5. DSP 鍔熻兘澧炲挤(qi谩ng)锛氶厤鍌欏皥鐢ㄤ箻娉曞櫒鍜岀疮鍔犲櫒妯″�婏紝鎻愬崌娴�榛�(di菐n)閬�(y霉n)绠楀拰鍥哄畾榛�(di菐n)閬�(y霉n)绠楁晥鐜�銆�
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銆�銆�7. 鍙�闈犳�ц垏鑰愮敤鎬э細鍏峰倷 ECC 鏍￠��(y脿n)鍔熻兘锛岀⒑淇濋棞(gu膩n)閸典换鍕�(w霉)鐠�(hu谩n)澧冧笅鐨勬暩(sh霉)鎿�(j霉)瀹屾暣鎬�銆�

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