EP4SGX360FH29C3N 鏅�(sh铆)闁擄細2023/7/28 12:00:26 闁辫畝锛�937

鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸瀷铏�(h脿o)	EP4SGX360FH29C3N
鎻忚堪	闆嗘垚闆昏矾FPGA 289 I/O 780HBGA
鍒嗛(l猫i)	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪)
鍒堕€犲晢	鑻辩壒鐖�
绯诲垪	Stratix?IV GX
鎵撳寘	鎵樼洡(p谩n)
闆朵欢鐙€鎱�(t脿i)	娲绘€�
闆诲-闆绘簮	0.87V?0.93V
宸ヤ綔婧害	0掳C?85掳C(TJ)
鍖呰/绠�	780-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	780-HBGA(33x33)
鍩烘湰闆朵欢铏�(h脿o)	EP4SGX360

鐢�(ch菐n)鍝佸湒鐗�

EP4SGX360FH29C3N

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓(l猫i)鍨�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪
绗﹀悎姝愮洘RoHS	鏄�
鐙€鎱�(t脿i)	杞�(zhu菐n)鍏�
鏈€澶ф檪(sh铆)閻橀牷鐜�	717.0鍏嗚但
JESD-30浠ｇ⒓	S-PBGA-B780
JESD-609浠ｇ⒓	1铏�(h脿o)
绺絉AM浣�	23105536
CLB鏁�(sh霉)閲�	14144.0
杓稿叆鏁�(sh霉)閲�	289.0
閭忚集鍠厓鏁�(sh霉)	353600.0
杓稿嚭鏁�(sh霉)閲�	289.0
绔瓙鏁�(sh霉)	780
鏈€浣庡伐浣滄韩搴�	0鈩�
鏈€楂樺伐浣滄韩搴�	85鈩�
绲勭箶	14144 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	245
闆绘簮	0.9,1.2 / 3,1.5,2.5
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
搴ч珮	3.4姣背
瀛愰(l猫i)鍒�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�(ch膿ng)	0.9浼�
鏈€灏忎緵闆婚浕澹�	0.87浼�
鏈€澶ч浕婧愰浕澹�	0.93浼�
瀹夎椤�(l猫i)鍨�	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆(j铆)	鍏朵粬
绲傜瀹屾垚	閷�/閵€/閵�(Sn / Ag / Cu)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅�(sh铆)闁揁宄板€煎洖娴佹韩搴︽渶澶у€�(绉�)	40
闀�(zh菐ng)搴�	33.0姣背
瀵害	33.0姣背
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü(sh霉)鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA780,28X28,40
鍖呰褰㈢媭	寤ｅ牬(ch菐ng)
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾�(shu艒)鏄�	33 X 33 MM锛岀劇(w煤)閴�锛孒BGA-780

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛(l猫i)

鐒�(w煤)閴涚媭鎱�(t脿i)/RoHS鐙€鎱�(t脿i)	鐒�(w煤)閴�/绗﹀悎RoHS
姘村垎鏁忔劅鎬ф按骞�(MSL)	3(168灏忔檪(sh铆))

鐗归粸(di菐n)

Stratix IV GX鍜孏T鍣ㄤ欢涓閬�(d谩)48鍊�(g猫)鍩轰簬CDR鐨勫叏闆欏伐鏀剁櫦(f膩)鍣�锛屽垎鍒ユ敮鎸侀珮閬�(d谩)8.5 Gbps鍜�11.3 Gbps鐨勬暩(sh霉)鎿�(j霉)閫熺巼銆�
鍏锋湁宓屽叆寮廝CIe纭琁P妯″鐨勫畬鏁碢CIe鍗�(xi茅)璀拌В姹烘柟妗�锛岄€欎簺妯″瀵�(sh铆)鐝�(xi脿n)PHY-MAC灞わ紝鏁�(sh霉)鎿�(j霉)閺堣矾灞ゅ拰浜嬪嫏(w霉)铏曠悊灞ゅ姛鑳�銆�
鍙法绋嬬殑鐧�(f膩)灏勬(j墨)闋�(y霉)鍔犻噸鍜屾帴鏀舵(j墨)鍧囪　闆昏矾锛屽彲瑁�(b菙)鍎熺墿鐞嗕粙璩�(zh矛)涓垏闋荤巼鏈夐棞(gu膩n)鐨勬悕鑰�銆�
姣忓€�(g猫)閫氶亾鐨勫吀鍨嬬墿鐞嗕粙璩�(zh矛)闄勪欢(PMA)鍔熻€楀垎鍒ョ偤3.125 Gbps鍜�100 mW锛�6.375 Gbps鏅�(sh铆)鐐�135 mW銆�
姣忚嚭(t谩i)瑷�(sh猫)鍌�72,600鑷�813,050绛夋晥LE銆�
7,370鑷�33,294 Kb鐨勫寮�(qi谩ng)鍨婽riMatrix瀛樺劜(ch菙)鍣�锛岀敱涓夌óRAM濉婂ぇ灏忕祫鎴愶紝鍙(sh铆)鐝�(xi脿n)鐪熸鐨勯洐绔彛瀛樺劜(ch菙)鍣ㄥ拰FIFO绶╂矕鍗€(q奴)銆�
楂橀€熸暩(sh霉)瀛椾俊铏�(h脿o)铏曠悊(DSP)妯″锛屾渶楂樺彲閰嶇疆鐐�9 x 9浣�锛�12 x 12浣�锛�18 x 18浣嶅拰36 x 36浣嶅叏绮惧害涔樻硶鍣�锛屾渶楂橀牷鐜囩偤600 MHz銆�
姣忓€�(g猫)瑷�(sh猫)鍌欐渶澶�16鍊�(g猫)鍏ㄥ眬鏅�(sh铆)閻�(GCLK)锛�88鍊�(g猫)鍗€(q奴)鍩熸檪(sh铆)閻�(RCLK)鍜�132鍊�(g猫)澶栧湇鏅�(sh铆)閻�(PCLK)銆�
鍙法绋嬮浕婧愭妧琛�(sh霉)锛屽彲鍦ㄦ渶澶х▼搴﹂檷浣庡姛鑰楃殑鍚屾檪(sh铆)鏈€澶у寲瑷�(sh猫)鍌欐€ц兘銆�
澶氶仈(d谩)1,120鍊�(g猫)鐢ㄦ埗(h霉)I / O寮曡叧甯冪疆鍦�24鍊�(g猫)妯″鍖朓 / O bank涓�锛岄€欎簺妯″鏀寔寤ｆ硾鐨勫柈绔拰宸垎I / O妯�(bi膩o)婧�(zh菙n)銆�
鏀寔澶氶仈(d谩)24鍊�(g猫)妯″鍖朓 / O bank 涓婄殑楂橀€熷閮ㄥ瓨鍎�(ch菙)鍣ㄦ帴鍙ｏ紝鍖呮嫭DDR锛孌DR2锛孌DR3 SDRAM锛孯LDRAM II锛孮DR II鍜孮DR II + SRAM
鍏锋湁涓茶鍣�/瑙ｄ覆鍣�(SERDES)锛屽嫊(d貌ng)鎱�(t脿i)鐩镐綅灏�(du矛)婧�(zh菙n)(DPA)鍜宻oft-CDR闆昏矾鐨勯珮閫烲VDS I / O鏀寔锛屾暩(sh霉)鎿�(j霉)閫熺巼楂橀仈(d谩)1.6 Gbps銆�銆�
鏀寔婧愬悓姝ョ附绶�(xi脿n)妯�(bi膩o)婧�(zh菙n)锛屽寘鎷琒GMII锛孏bE锛孲PI-4 闅庢2(POS-PHY绱�(j铆)鍒�4)锛孲FI-4.1锛孹SBI锛孶TOPIA IV锛孨PSI鍜孋SIX-L1銆�
Stratix IV E鍣ㄤ欢鐨勫紩鑵虫帓鍒�锛屾棬鍦ㄥ厑瑷卞皣瑷�(sh猫)瑷�(j矛)寰濻tratix III 閬风Щ鍒癝tratix IV E锛岃€屽皪(du矛)PCB鐨勫奖闊挎渶灏�銆�
灏�(zhu膩n)鐢ㄩ浕璺敮鎸佹祦琛岀殑涓茶鍗�(xi茅)璀扮殑鐗╃悊灞ゅ姛鑳�锛屼緥濡侾CI Express(PCIe)(PIPE)Gen1鍜孏en2锛孏bps浠ュお缍�(w菐ng)(GbE)锛屼覆琛孯apidIO锛孲ONET / SDH锛孹AUI / HiGig锛�(OIF)CEI-6G锛孲D / HD / 3G-SDI锛屽厜绾栭€氶亾锛孲FI-5鍜孖nterlaken銆�