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EP4SGX180KF40C5N 鏄竴娆剧敱 Intel锛堢従(xi脿n)鐐� Microchip Technology锛夊埗閫犵殑 Stratix IV GX 绯诲垪 FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛�銆傝┎绯诲垪鑺墖涓昏闈㈠悜楂樻€ц兘瑷堢畻銆侀€氫俊鍩虹(ch菙)瑷�(sh猫)鏂�銆佽粛浜嬪拰鑸┖鑸ぉ绛夋噳(y墨ng)鐢ㄩ牁(l菒ng)鍩�銆係tratix IV GX 绯诲垪閲囩敤浜� 40 nm 鍒剁▼宸ヨ棟锛屽叿鏈夐珮閭忚集瀵嗗害銆侀珮閫熶覆琛屾敹鐧�(f膩)鍣ㄤ互鍙婅睈瀵岀殑 DSP 璩囨簮銆�
銆€銆€EP4SGX180KF40C5N 鎻愪緵浜嗗閬�(d谩) 180K 鍊嬮倧杓柈鍏冿紝鏀寔澶氱ó I/O 妯�(bi膩o)婧�(zh菙n)锛屽苟涓斿収(n猫i)缃簡楂樻€ц兘鐨勭‖鏍� IP 妯″锛屼緥濡� PCIe 鍜岄珮閫熸敹鐧�(f膩)鍣�锛屼互婊胯冻寰�(f霉)闆滅郴绲�(t菕ng)瑷�(sh猫)瑷堢殑闇€姹傘€�

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鍨嬭櫉锛欵P4SGX180KF40C5N
銆€銆€鍝佺墝锛欼ntel (Microchip Technology)
銆€銆€绯诲垪锛歋tratix IV GX
銆€銆€鍒剁▼宸ヨ棟锛�40nm
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細180K
銆€銆€RAM 璩囨簮锛氱磩 7.2 Mb
銆€銆€DSP 妯″鏁�(sh霉)閲忥細360
銆€銆€鏀剁櫦(f膩)鍣ㄩ€氶亾鏁�(sh霉)閲忥細36
銆€銆€鏀剁櫦(f膩)鍣ㄩ€熺巼鑼冨湇锛�600 Mbps 鑷� 11.3 Gbps
銆€銆€I/O 鏁�(sh霉)閲忥細鏈€澶� 940
銆€銆€灏佽椤炲瀷锛欶BGA 1196
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆€銆€渚涢浕闆诲锛�1.0V 鏍稿績闆诲锛�1.8V/2.5V I/O 闆诲

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EP4SGX180KF40C5N 鐨勪富瑕佺壒鎬у寘鎷細
銆€銆€1. 楂樻€ц兘 FPGA 鏋舵(g貌u)锛氶噰鐢ㄥ厛閫�(j矛n)鐨� 40nm 宸ヨ棟锛屽叿鍌欓珮閭忚集瀵嗗害鍜屼綆鍔熻€楃壒榛�銆�
銆€銆€2. 鍏�(n猫i)缃‖鏍� IP锛氶泦鎴� PCIe 纭牳妯″鍜屾敮鎸侀珮閬�(d谩) 11.3 Gbps 鐨勯珮閫熸敹鐧�(f膩)鍣�锛岄仼鍚堥渶瑕佸ぇ閲忔暩(sh霉)鎿�(j霉)鍌宠几?sh霉)鑶�?y墨ng)鐢ㄥ牬鏅�銆�
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銆€銆€4. 澶氭ǎ鍖栫殑 I/O 鏀寔锛氬吋瀹瑰绋(bi膩o)婧�(zh菙n)锛屽 LVDS銆丩VPECL 鍜� HSTL锛屾豢瓒充笉鍚屾帴鍙ｉ渶姹傘€�
銆€銆€5. 澧炲挤(qi谩ng)鐨勫畨鍏ㄦ€э細鏀寔 AES 鍔犲瘑銆丷SA 瑾�(r猫n)璀夌瓑鍔熻兘锛屼繚闅滆ō(sh猫)瑷堢殑瀹夊叏鎬у拰鐭ヨ瓨鐢�(ch菐n)娆�(qu谩n)淇濊(h霉)銆�
銆€銆€6. 鏄撶敤鐨勮ō(sh猫)瑷堝伐鍏凤細閰嶅悎 Quartus II 杌熶欢锛屾彁渚涘緸瑷�(sh猫)瑷堣几鍏ュ埌椹楄瓑鐨勫畬鏁撮枊鐧�(f膩)鐠�(hu谩n)澧�銆�

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EP4SGX180KF40C5N 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆€銆€1. 閫氫俊瑷�(sh猫)鍌欙細濡傝矾鐢卞櫒銆佷氦鎻涙(j墨)鍜屽熀绔欙紝鐢ㄤ簬瀵︾従(xi脿n)楂橀€熸暩(sh霉)鎿�(j霉)鍌宠几鍜屼俊铏熻檿鐞�銆�
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